#
6e7df1d1 |
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10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8214b772 |
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02-Dec-2022 |
Tom Rini <trini@konsulko.com> |
T104xRDB: Remove non-TARGET_T1042D4RDB variants At this point only the TARGET_T1042D4RDB variant of this is supported in tree, so remove the remaining parts of the other platforms. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a581af2 |
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02-Dec-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_FLASH_SPANSION_S29WS_N et al to Kconfig This converts the following to Kconfig: CONFIG_FLASH_SPANSION_S29WS_N CONFIG_FLASH_VERIFY CONFIG_FSL_FM_10GEC_REGULAR_NOTATION CONFIG_FSL_ISBC_KEY_EXT CONFIG_FSL_TRUST_ARCH_v1 CONFIG_FSL_SDHC_V2_3 CONFIG_MAX_DSP_CPUS CONFIG_MIU_2BIT_INTERLEAVED CONFIG_SERIAL_BOOT CONFIG_SPI_BOOTING CONFIG_X86EMU_RAW_IO Signed-off-by: Tom Rini <trini@konsulko.com> |
#
65cc0e2a |
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16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
f6c1f917 |
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25-Jun-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_SYS_FSL_CPC et al to Kconfig This converts the following to Kconfig: CONFIG_SYS_FSL_CPC CONFIG_SYS_CPC_REINIT_F Signed-off-by: Tom Rini <trini@konsulko.com> |
#
f4cd75e9 |
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17-Jun-2022 |
Tom Rini <trini@konsulko.com> |
powerpc: Clean up CHAIN_OF_TRUST related options As things stand currently, there is only one PowerPC platform that enables the options for CHAIN_OF_TRUST. From the board header files, remove a number of never-set options. Remove board specific values from arch/powerpc/include/asm/fsl_secure_boot.h as well. Rework include/config_fsl_chain_trust.h to not abuse the CONFIG namespace for constructing CHAIN_BOOT_CMD. Migrate all of the configurable addresses to Kconfig. If any platforms are re-introduced with secure boot support, everything required should still be here, but now in Kconfig, or requires migration of an option to Kconfig. Cc: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
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5aad0a14 |
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17-Jun-2022 |
Tom Rini <trini@konsulko.com> |
fsl_validate: Migrate SPL_UBOOT_KEY_HASH to Kconfig Move setting of SPL_UBOOT_KEY_HASH to a non-NULL value to Kconfig. As part of this, change fsl_secboot_validate(...) to check that it is passed a non-empty string, rather than non-NULL. Cc: Peng Fan <peng.fan@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Kshitiz Varshney <kshitiz.varshney@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
601483ff |
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16-Jun-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_SYS_FSL_SFP_BE et al to Kconfig This converts the following to Kconfig: CONFIG_KEY_REVOCATION CONFIG_SYS_FSL_SFP_BE CONFIG_SYS_FSL_SFP_LE CONFIG_SYS_FSL_SFP_VER_3_0 CONFIG_SYS_FSL_SFP_VER_3_2 CONFIG_SYS_FSL_SFP_VER_3_4 CONFIG_SYS_FSL_SRK_LE This partly means making sure to enable SYS_FSL_ERRATUM_A007186 only for when CHAIN_OF_TRUST is enabled. Signed-off-by: Tom Rini <trini@konsulko.com> |
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c9f85187 |
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16-Jun-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_SYS_FSL_SEC_MON et al to Kconfig This converts the following to Kconfig: CONFIG_SYS_FSL_SEC_MON CONFIG_SYS_FSL_SEC_MON_BE CONFIG_SYS_FSL_SEC_MON_LE Signed-off-by: Tom Rini <trini@konsulko.com> |
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ec6b37ce |
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23-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove T4160RDB board This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it. As this is the last ARCH_T4160 platform, remove that support as well. Signed-off-by: Tom Rini <trini@konsulko.com> |
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6c3d9933 |
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14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove T1023RBD boards and T1024RDB_SECURE_BOOT These boards have not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove them. As this is the only ARCH_T1023 platform left, remove that support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
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008e9965 |
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14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove many T104x boards These boards have not been converted to CONFIG_DM_PCI, CONFIG_DM_USB or in some cases CONFIG_DM itself by the deadline. Remove them. Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a99dab1d |
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20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove Cyrus_P5020 and P5040 boards These boards have not been converted to CONFIG_DM_MMC by the deadline. Remove them. As the P5020 is the last ARCH_P5020 platform, remove that support as well. Cc: Andy Fleming <afleming@gmail.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
bf85995a |
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20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove TARGET_T1040QDS references The TARGET_T1040QDS platforms have been removed already, drop some remaining references in the code. Signed-off-by: Tom Rini <trini@konsulko.com> |
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bef18454 |
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07-Nov-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
freescale/powerpc: Rename the config CONFIG_SECURE_BOOT name Rename the CONFIG_SECURE_BOOT name to CONFIG_NXP_ESBC to avoid conflicts with UEFI secure boot. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ea7971f7 |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_CMD_ESBC_VALIDATE to Kconfig This converts the following to Kconfig: CONFIG_CMD_ESBC_VALIDATE Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
089df18b |
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14-May-2017 |
Tom Rini <trini@konsulko.com> |
lib: move hash CONFIG options to Kconfig Commit 94e3c8c4fd7b ("crypto/fsl - Add progressive hashing support using hardware acceleration.") created entries for CONFIG_SHA1, CONFIG_SHA256, CONFIG_SHA_HW_ACCEL, and CONFIG_SHA_PROG_HW_ACCEL. However, no defconfig has migrated to it. Complete the move by first adding additional logic to various Kconfig files to select this when required and then use the moveconfig tool. In many cases we can select these because they are required to implement other drivers. We also correct how we include the various hashing algorithms in SPL. This commit was generated as follows (after Kconfig additions): [1] tools/moveconfig.py -y SHA1 SHA256 SHA_HW_ACCEL [2] tools/moveconfig.py -y SHA_PROG_HW_ACCEL Note: We cannot move SHA_HW_ACCEL and SHA_PROG_HW_ACCEL simultaneously because there is dependency between them. Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com> Cc: Naveen Burmi <NaveenBurmi@freescale.com> Cc: Po Liu <po.liu@freescale.com> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Priyanka Jain <Priyanka.Jain@freescale.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Chander Kashyap <k.chander@samsung.com> Cc: Steve Rae <steve.rae@raedomain.com> Cc: Dirk Eibach <eibach@gdsys.de> Cc: Feng Li <feng.li_2@nxp.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Sumit Garg <sumit.garg@nxp.com> Cc: Mingkai Hu <Mingkai.Hu@freescale.com> Cc: York Sun <york.sun@nxp.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Akshay Saraswat <akshay.s@samsung.com> Cc: Heiko Schocher <hs@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
c04b9b34 |
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26-Apr-2017 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_CMD_BLOB to Kconfig This converts the following to Kconfig: CONFIG_CMD_BLOB Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Add imply CMD_BLOB under CHAIN_OF_TRUST] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
0645c23a |
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30-Mar-2017 |
VINITHA PILLAI <vinitha.pillai@nxp.com> |
powerpc: T1042RDB: SECURE BOOT: Remove CONFIG_CMD_BLOB from SPL compilation BLOB feature is not required during SPL compilation. Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
28522678 |
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01-Mar-2017 |
Tom Rini <trini@konsulko.com> |
Freescale/NXP: Migrate CONFIG_FSL_CAAM to defconfigs In some cases this is absolutely required, so select this for some secure features. This also requires migration of RSA_FREESCALE_EXP Cc: Ruchika Gupta <ruchika.gupta@nxp.com> Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com> Cc: Naveen Burmi <NaveenBurmi@freescale.com> Cc: Po Liu <po.liu@freescale.com> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Priyanka Jain <Priyanka.Jain@freescale.com> Cc: Sumit Garg <sumit.garg@nxp.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Feng Li <feng.li_2@nxp.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Mingkai Hu <Mingkai.Hu@freescale.com> Cc: York Sun <york.sun@nxp.com> Cc: Saksham Jain <saksham.jain@nxp.freescale.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
88077715 |
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22-Jan-2017 |
Tom Rini <trini@konsulko.com> |
NXP: Introduce board/freescale/common/Kconfig and migrate CHAIN_OF_TRUST Introduce board/freescale/common/Kconfig so that we have a single place for CONFIG options that are shared between ARM and PowerPC NXP platforms. Cc: York Sun <york.sun@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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3788b451 |
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21-Jan-2017 |
Jagan Teki <jagan@openedev.com> |
config: Move CONFIG_BOARD_LATE_INIT to defconfigs Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jagan@openedev.com> |
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a1055038 |
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28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T104xQDS: Remove macro CONFIG_T104xD4QDS Remove this macro. It was added by e622d9ed but actually wasn't used. Signed-off-by: York Sun <york.sun@nxp.com> |
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86e0a313 |
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28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T2080RDB: Remove macro CONFIG_T2080RDB Use TARGET_T2080RDB from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com> |
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80d26188 |
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28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T2080QDS: Remove macro T2080QDS Use TARGET_T2080QDS from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com> |
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f4f66940 |
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28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1040QDS: Remove macro CONFIG_T1040QDS Use TARGET_T1040QDS from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com> |
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673c01c7 |
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21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4240QDS: Remove macro CONFIG_T4240QDS Use CONFIG_TARGET_T4240QDS instead. Signed-off-by: York Sun <york.sun@nxp.com> |
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9c21d06c |
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21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4160QDS: Separate from T4240QDS in Kconfig Use TARGET_T4160QDS to simplify Kconfig options. Signed-off-by: York Sun <york.sun@nxp.com> |
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78e56995 |
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21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T104xRDB: Remove macro CONFIG_T104xRDB and T104xD4RDB CONFIG_T104xRDB is defined in T104xRDB.h, so it is always enabled for all T1040RDB, T1040D4RDB, T1042RDB, T1042D4RDB, T1042RDB_PI. CONFIG_T104XD4RDB is defined for all T1040D4RDB, T1042D4RDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e5d5f5a8 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1024: Remove macro CONFIG_PPC_T1024 Replace CONFIG_PPC_T1024 with ARCH_T1024 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
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5ff3f41d |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1023: Remove macro CONFIG_PPC_T1023 Replace CONFIG_PPC_T1023 with ARCH_T1023 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
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d46a4a13 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: B4860QDS: Remove macro CONFIG_B4860QDS Use CONFIG_TARGET_B4860QDS instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
95390360 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P5040: Remove macro CONFIG_P5040 Replace CONFIG_P5040 with ARCH_P5040 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
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cefe11cd |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P5020: Remove macro CONFIG_PPC_P5020 Replace CONFIG_PPC_P5020 with ARCH_P5020 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
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e71372cb |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P4080: Remove macro CONFIG_PPC_P4080 Replace CONFIG_PPC_P4080 with ARCH_P4080 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5e5fdd2d |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P3041: Remove macro CONFIG_PPC_P3041 Replace CONFIG_PPC_P3041 with ARCH_P3041 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
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ce040c83 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P2041: Remove macro CONFIG_PPC_P2041 Replace CONFIG_PPC_P2041 with ARCH_P2041 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
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ebccf255 |
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16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: C29XPCIE: Remove macro CONFIG_C29XPCIE Use CONFIG_TARGET_C29XPCIE instead. Signed-off-by: York Sun <york.sun@nxp.com> |
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a202b9f8 |
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15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: BSC9132QDS: Remove CONFIG_BSC9132QDS macro Use CONFIG_TARGET_BSC9132QDS from Kconfig option, remove CONFIG_BSC9132QDS macro. Signed-off-by: York Sun <york.sun@nxp.com> |
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d3662dff |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_SPL_DRIVERS_MISC_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org> |
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d3e7e2b2 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_SPL_HASH_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
dbdaeee4 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_SPL_CRYPTO_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d3c1f467 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Move existing use of CONFIG_SPL_RSA to Kconfig A few boards define this in a header file which is incorrect. It means that Kconfig options that rely on this cannot be used. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3433a693 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Move existing use of CONFIG_SPL_DM to Kconfig A few boards define this in a header file which is incorrect. It means that Kconfig options that rely on this cannot be used. Move it. Note that quite a few boards defined this options but do not appear to actually use SPL: BSC9132QDS_NOR_DDRCLK100_SECURE BSC9132QDS_NOR_DDRCLK133_SECURE BSC9132QDS_SDCARD_DDRCLK100_SECURE BSC9132QDS_SDCARD_DDRCLK133_SECURE BSC9132QDS_SPIFLASH_DDRCLK100_SECURE BSC9132QDS_SPIFLASH_DDRCLK133_SECURE C29XPCIE_NOR_SECBOOT P1010RDB-PA_36BIT_NAND_SECBOOT P1010RDB-PA_36BIT_SPIFLASH_SECBOOT P1010RDB-PA_NAND_SECBOOT P1010RDB-PA_NOR_SECBOOT P1010RDB-PB_36BIT_NOR_SECBOOT P1010RDB-PB_36BIT_SPIFLASH_SECBOOT P1010RDB-PB_NAND_SECBOOT P1010RDB-PB_NOR_SECBOOT P3041DS_SECURE_BOOT P4080DS_SECURE_BOOT P5020DS_NAND_SECURE_BOOT P5040DS_SECURE_BOOT T1023RDB_SECURE_BOOT T1024QDS_DDR4_SECURE_BOOT T1024QDS_SECURE_BOOT T1024RDB_SECURE_BOOT T1040RDB_SECURE_BOOT T1042D4RDB_SECURE_BOOT T1042RDB_SECURE_BOOT T2080QDS_SECURE_BOOT T2080RDB_SECURE_BOOT T4160QDS_SECURE_BOOT T4240QDS_SECURE_BOOT ls1021aqds_nor_SECURE_BOOT ls1021atwr_nor_SECURE_BOOT ls1043ardb_SECURE_BOOT For these boards CONFIG_SPL_DM will no-longer be defined in SPL. But since they apparently don't have an SPL, this should not matter. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
b63f8a43 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
arm: fsl: Adjust ordering of #ifndef CONFIG_SPL_BUILD The secure boot header files incorrectly define SPL options only if CONFIG_SPL_BUILD is defined. This means that the options are only enabled in an SPL build, and not with a normal 'make xxx_defconfig'. This means that moveconfig.py cannot work, since it sees the options as disabled even when they may be manually enabled in an SPL build. Fix this by changing the order. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
69d4b48c |
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14-Jun-2016 |
Sumit Garg <sumit.garg@nxp.com> |
SECURE_BOOT: Enable SD as a source for bootscript Add support for reading bootscript and bootscript header from SD. Also renamed macros *_FLASH to *_DEVICE to represent SD alongwith NAND and NOR flash. Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
aa36c84e |
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13-Jul-2016 |
Sumit Garg <sumit.garg@nxp.com> |
powerpc/mpc85xx: T104x: Add nand secure boot target For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In non-secure boot scenario from NAND, this address will map to CPC configured as SRAM. But in case of secure boot, this default address always maps to IBR (Internal Boot ROM). The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. For secure boot target from NAND, the text base for SPL is kept same as non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000) As a the virtual and physical address of CPC would be different. The virtual address 0xFFFx_xxxx needs to be mapped to physical address 0xBFFx_xxxx. Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000 and update DCFG SCRTACH1 register with location of Header required for secure boot. The changes are similar to commit 467a40dfe35f48d830f01a72617207d03ca85b4d powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC is only 256K and thus SPL framework is used. The changes are only applicable for SPL U-Boot running out of CPC SRAM and not the next level U-Boot loaded on DDR. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
8f01397b |
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13-Jul-2016 |
Sumit Garg <sumit.garg@nxp.com> |
powerpc/mpc85xx: SECURE BOOT- Enable chain of trust in SPL As part of Chain of Trust for Secure boot, the SPL U-Boot will validate the next level U-boot image. Add a new function spl_validate_uboot to perform the validation. Enable hardware crypto operations in SPL using SEC block. In case of Secure Boot, PAMU is not bypassed. For allowing SEC block access to CPC configured as SRAM, configure PAMU. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
73223f0e |
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22-Feb-2016 |
Simon Glass <sjg@chromium.org> |
Kconfig: Move CONFIG_FIT and related options to Kconfig There are already two FIT options in Kconfig but the CONFIG options are still in the header files. We need to do a proper move to fix this. Move these options to Kconfig and tidy up board configuration: CONFIG_FIT CONFIG_OF_BOARD_SETUP CONFIG_OF_SYSTEM_SETUP CONFIG_FIT_SIGNATURE CONFIG_FIT_BEST_MATCH CONFIG_FIT_VERBOSE CONFIG_OF_STDOUT_VIA_ALIAS CONFIG_RSA Unfortunately the first one is a little complicated. We need to make sure this option is not enabled in SPL by this change. Also this option is enabled automatically in the host builds by defining CONFIG_FIT in the image.h file. To solve this, add a new IMAGE_USE_FIT #define which can be used in files that are built on the host but must also build for U-Boot and SPL. Note: Masahiro's moveconfig.py script is amazing. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Add microblaze change, various configs/ re-applies] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
9e971632 |
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22-Feb-2016 |
Simon Glass <sjg@chromium.org> |
freescale: Remove CONFIG_DM from header files Kconfig options must defined in the defconfig files. Since RSA_SOFTWARE_EXP relies on CONFIG_DM, unless it is set in kconfig we cannot enable RSA. Remove the hacks which enable CONFIG_DM in header files and update the defconfig. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d0a6d7ce |
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22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: enable chain of trust for PowerPC platforms Chain of Trust is enabled for PowerPC platforms for Secure Boot. CONFIG_BOARD_LATE_INIT is defined. In board_late_init(), fsl_setenv_chain_of_trust() is called which will perform the following: - If boot mode is non-secure, return (No Change) - If boot mode is secure, set the following environmet variables: bootdelay = 0 (To disable Boot Prompt) bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
bdc22074 |
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22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: split the secure boot functionality in two parts There are two phases in Secure Boot 1. ISBC: In BootROM, validate the BootLoader (U-Boot). 2. ESBC: In U-Boot, continuing the Chain of Trust by validating and booting LINUX. For ESBC phase, there is no difference in SoC's based on ARM or PowerPC cores. But the exit conditions after ISBC phase i.e. entry conditions for U-Boot are different for ARM and PowerPC. PowerPC: If Secure Boot is executed, a separate U-Boot target is required which must be compiled with a diffrent Text Base as compared to Non-Secure Boot. There are some LAW and TLB settings which are required specifically for Secure Boot scenario. ARM: ARM based SoC's have a fixed memory map and exit conditions from BootROM are same irrespective of boot mode (Secure or Non-Secure). Thus the current Secure Boot functionlity has been split into two parts: CONFIG_CHAIN_OF_TRUST This will have the following functionality as part of U-Boot: 1. Enable commands like esbc_validate, esbc_halt 2. Change the environment settings based on bootmode, determined at run time: - If bootmode is non-secure, no change - If bootmode is secure, set the following: - bootdelay = 0 (Don't give boot prompt) - bootcmd = Validate and execute the bootscript. CONFIG_SECURE_BOOT This is defined only for creating a different compile time target for secure boot. Traditionally, both these functionalities were defined under CONFIG_SECURE_BOOT. This patch is aimed at removing the requirement for a separate Secure Boot target for ARM based SoC's. CONFIG_CHAIN_OF_TRUST will be defined and boot mode will be determine at run time. Another Security Requirement for running CHAIN_OF_TRUST is that U-Boot environemnt must not be picked from flash/external memory. This cannot be done based on bootmode at run time in current U-Boot architecture. Once this dependency is resolved, no separate SECURE_BOOT target will be required for ARM based SoC's. Currently, the only code under CONFIG_SECURE_BOOT for ARM SoC's is defining CONFIG_ENV_IS_NOWHERE Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
74eecd82 |
|
22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: include/configs: move definition of CONFIG_CMD_BLOB CONFIG_CMD_BLOB must be defined in case of Secure Boot. It was earlier defined in all config files. The definition has been moved to a common file which is included by all configs. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2ed948f4 |
|
31-Jul-2015 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
SECURE_BOOT: Disable IE Key feature for RAMBOOT ISBC Key Extension feature is not applicable for RAMBOOT as there is no way to retrieve the CSF Header and validated IE Key table from SRAM once CPC has been disabled. The feature is only applicable in case of NOR SECURE BOOT. Code Cleanup: The SECURE_BOOT specific defines have been moved from arch-ls102xa/config.h to arm/include/asm/fsl_secure_boot.h Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
5050f6f0 |
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15-Jun-2015 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT-Copy Boot Script on RAM For running Chain of Trust when doing Secure Boot from NAND, the Bootscript header and bootscript must be copied from NAND to RAM(DDR). The addresses and commands for the same have been defined. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
467a40df |
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15-Jun-2015 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 Secure Boot Target is added for NAND for P3041. For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In case of secure boot, this default address maps to Boot ROM. The Boot ROM code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is configured as SRAM. U-Boot binary will be located on SRAM configured at address 0xBFF00000. In the U-Boot code, TLB entries are created to map the virtual address 0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e622d9ed |
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26-Mar-2015 |
gaurav rana <gaurav.rana@freescale.com> |
powerpc/T104xD4: Add Secure boot support for T104xD4RDB platforms defconfig files are added and SFP version for these platforms is updated. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
98cb0efd |
|
10-Mar-2015 |
gaurav rana <gaurav.rana@freescale.com> |
Add bootscript support to esbc_validate. 1. Default environment will be used for secure boot flow which can't be edited or saved. 2. Command for secure boot is predefined in the default environment which will run on autoboot (and autoboot is the only option allowed in case of secure boot) and it looks like this: #define CONFIG_SECBOOT \ "setenv bs_hdraddr 0xe8e00000;" \ "esbc_validate $bs_hdraddr;" \ "source $img_addr;" \ "esbc_halt;" #endif 3. Boot Script can contain esbc_validate commands and bootm command. Uboot source command used in default secure boot command will run the bootscript. 4. Command esbc_halt added to ensure either bootm executes after validation of images or core should just spin. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e04916a7 |
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26-Feb-2015 |
gaurav rana <gaurav.rana@freescale.com> |
SECURE_BOOT : enable esbc_validate command for powerpc and arm platforms. esbc_validate command uses various IP Blocks: Security Monitor, CAAM block and SFP registers. Hence the respective CONFIG's are enabled. Apart from these CONFIG_SHA_PROG_HW_ACCEL and CONFIG_RSA are also enabled. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
b3f0f632 |
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12-Dec-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: Define PBI Flash Base for C29XPCIE Secure Boot CONFIG_SYS_PBI_FLASH_BASE is defined for Secure Boot on C29X Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
f6050790 |
|
24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/mpc85xx: Add T1024/T1023 SoC support Add support for Freescale T1024/T1023 SoC. The T1024 SoC includes the following function and features: - Two 64-bit Power architecture e5500 cores, up to 1.4GHz - private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC) - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration - Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI) - High-speed peripheral interfaces - Three PCI Express 2.0 controllers - Additional peripheral interfaces - One SATA 2.0 controller - Two USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/eSDHC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Two 8-channel DMA engines - Multicore programmable interrupt controller (PIC) - LCD interface (DIU) with 12 bit dual data rate - QUICC Engine block supporting TDM, HDLC, and UART - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T1024 and T1023: Feature T1024 T1023 QUICC Engine: yes no DIU: yes no Deep Sleep: yes no I2C controller: 4 3 DDR: 64-bit 32-bit IFC: 32-bit 28-bit Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e47c2a68 |
|
22-Apr-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080RDB Secure Boot Target is added for T2080RDB Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080RDB. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> |
#
40678159 |
|
22-Apr-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- secure boot target for t1040rdb T1040RDB.h file is removed and a unified file T104xRDB.h is created. Hence macro CONFIG_T1040 is renamed to CONFIG_T104x. Signed-off-by: Gaurav Kumar Rana <gaurav.rana@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> |
#
2d8db6d3 |
|
18-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T1040QDS and T1040RDB Secure Boot Target is added for T1040QDS and T1040RDB Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T1040QDS and CONFIG_T1040RDB Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
ca4819df |
|
18-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080QDS Secure Boot Target is added for T2080QDS Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080QDS. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
796a7810 |
|
18-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T4240QDS and T4160QDS Secure Boot Target is added for T4240QDS and T4160QDS Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T4240QDS. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
fb4a2409 |
|
18-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS Changes: 1. L2 cache is being invalidated by Boot ROM code for e6500 core. So removing the invalidation from start.S 2. Clear the LAW and corresponding configuration for CPC. Boot ROM code uses it as hosekeeping area. 3. For Secure boot, CPC is configured as SRAM and used as house keeping area. This configuration is to be disabled once in uboot. Earlier this disabling of CPC as SRAM was happening in cpu_init_r. As a result cache invalidation function was getting skipped in case CPC is configured as SRAM.This was causing random crashes. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
f978f7c2 |
|
11-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for BSC9132QDS Add NOR, SPI and SD secure boot targets for BSC9132QDS. Changes: - Debug TLB entry is not required for Secure Boot Target. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
0d2cff2d |
|
21-Aug-2013 |
Po Liu <po.liu@freescale.com> |
powerpc: add CONFIG_SECURE_BOOT condition into fsl_secure_boot.h This patch is for board config file not to add CONFIG_SECURE_BOOT condition for include the asm/fsl_secure_boot.h. Signed-off-by: Po Liu <Po.Liu@freescale.com> |
#
1a459660 |
|
08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
39bdaff4 |
|
25-Mar-2013 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
SECURE BOOT - Removed deletion of TLB entries code Boot ROM code creates TLB entries for 3.5G space before entering the u-boot. Earlier we were deleting these entries after early initialization of CPU. In recent past, code has been added to invalidate all these entries before relocation of u-boot code. So this code to delete TLB entries after CPU initialization is no longer required. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Acked-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
7065b7d4 |
|
15-Dec-2010 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
powerpc/p4080: Add support for secure boot flow Pre u-boot Flow: 1. User loads the u-boot image in flash 2. PBL/Configuration word is used to create LAW for Flash at 0xc0000000 (Please note that ISBC expects all these addresses, images to be validated, entry point etc within 0 - 3.5G range) 3. ISBC validates the u-boot image, and passes control to u-boot at 0xcffffffc. Changes in u-boot: 1. Temporarily map CONFIG_SYS_MONITOR_BASE to the 1M CONFIG_SYS_PBI_FLASH_WINDOW in AS=1. (The CONFIG_SYS_PBI_FLASH_WINDOW is the address map for the flash created by PBL/configuration word within 0 - 3.5G memory range. The u-boot image at this address has been validated by ISBC code) 2. Remove TLB entries for 0 - 3.5G created by ISBC code 3. Remove the LAW entry for the CONFIG_SYS_PBI_FLASH_WINDOW created by PBL/configuration word after switch to AS = 1 Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com> Acked-by: Wood Scott-B07421 <B07421@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
8214b772 |
|
02-Dec-2022 |
Tom Rini <trini@konsulko.com> |
T104xRDB: Remove non-TARGET_T1042D4RDB variants At this point only the TARGET_T1042D4RDB variant of this is supported in tree, so remove the remaining parts of the other platforms. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a581af2 |
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02-Dec-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_FLASH_SPANSION_S29WS_N et al to Kconfig This converts the following to Kconfig: CONFIG_FLASH_SPANSION_S29WS_N CONFIG_FLASH_VERIFY CONFIG_FSL_FM_10GEC_REGULAR_NOTATION CONFIG_FSL_ISBC_KEY_EXT CONFIG_FSL_TRUST_ARCH_v1 CONFIG_FSL_SDHC_V2_3 CONFIG_MAX_DSP_CPUS CONFIG_MIU_2BIT_INTERLEAVED CONFIG_SERIAL_BOOT CONFIG_SPI_BOOTING CONFIG_X86EMU_RAW_IO Signed-off-by: Tom Rini <trini@konsulko.com> |
#
65cc0e2a |
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16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
f6c1f917 |
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25-Jun-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_SYS_FSL_CPC et al to Kconfig This converts the following to Kconfig: CONFIG_SYS_FSL_CPC CONFIG_SYS_CPC_REINIT_F Signed-off-by: Tom Rini <trini@konsulko.com> |
#
f4cd75e9 |
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17-Jun-2022 |
Tom Rini <trini@konsulko.com> |
powerpc: Clean up CHAIN_OF_TRUST related options As things stand currently, there is only one PowerPC platform that enables the options for CHAIN_OF_TRUST. From the board header files, remove a number of never-set options. Remove board specific values from arch/powerpc/include/asm/fsl_secure_boot.h as well. Rework include/config_fsl_chain_trust.h to not abuse the CONFIG namespace for constructing CHAIN_BOOT_CMD. Migrate all of the configurable addresses to Kconfig. If any platforms are re-introduced with secure boot support, everything required should still be here, but now in Kconfig, or requires migration of an option to Kconfig. Cc: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5aad0a14 |
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17-Jun-2022 |
Tom Rini <trini@konsulko.com> |
fsl_validate: Migrate SPL_UBOOT_KEY_HASH to Kconfig Move setting of SPL_UBOOT_KEY_HASH to a non-NULL value to Kconfig. As part of this, change fsl_secboot_validate(...) to check that it is passed a non-empty string, rather than non-NULL. Cc: Peng Fan <peng.fan@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Kshitiz Varshney <kshitiz.varshney@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
601483ff |
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16-Jun-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_SYS_FSL_SFP_BE et al to Kconfig This converts the following to Kconfig: CONFIG_KEY_REVOCATION CONFIG_SYS_FSL_SFP_BE CONFIG_SYS_FSL_SFP_LE CONFIG_SYS_FSL_SFP_VER_3_0 CONFIG_SYS_FSL_SFP_VER_3_2 CONFIG_SYS_FSL_SFP_VER_3_4 CONFIG_SYS_FSL_SRK_LE This partly means making sure to enable SYS_FSL_ERRATUM_A007186 only for when CHAIN_OF_TRUST is enabled. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
c9f85187 |
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16-Jun-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_SYS_FSL_SEC_MON et al to Kconfig This converts the following to Kconfig: CONFIG_SYS_FSL_SEC_MON CONFIG_SYS_FSL_SEC_MON_BE CONFIG_SYS_FSL_SEC_MON_LE Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ec6b37ce |
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23-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove T4160RDB board This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it. As this is the last ARCH_T4160 platform, remove that support as well. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
6c3d9933 |
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14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove T1023RBD boards and T1024RDB_SECURE_BOOT These boards have not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove them. As this is the only ARCH_T1023 platform left, remove that support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
008e9965 |
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14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove many T104x boards These boards have not been converted to CONFIG_DM_PCI, CONFIG_DM_USB or in some cases CONFIG_DM itself by the deadline. Remove them. Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a99dab1d |
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20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove Cyrus_P5020 and P5040 boards These boards have not been converted to CONFIG_DM_MMC by the deadline. Remove them. As the P5020 is the last ARCH_P5020 platform, remove that support as well. Cc: Andy Fleming <afleming@gmail.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
bf85995a |
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20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove TARGET_T1040QDS references The TARGET_T1040QDS platforms have been removed already, drop some remaining references in the code. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
bef18454 |
|
07-Nov-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
freescale/powerpc: Rename the config CONFIG_SECURE_BOOT name Rename the CONFIG_SECURE_BOOT name to CONFIG_NXP_ESBC to avoid conflicts with UEFI secure boot. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
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ea7971f7 |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_CMD_ESBC_VALIDATE to Kconfig This converts the following to Kconfig: CONFIG_CMD_ESBC_VALIDATE Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
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089df18b |
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14-May-2017 |
Tom Rini <trini@konsulko.com> |
lib: move hash CONFIG options to Kconfig Commit 94e3c8c4fd7b ("crypto/fsl - Add progressive hashing support using hardware acceleration.") created entries for CONFIG_SHA1, CONFIG_SHA256, CONFIG_SHA_HW_ACCEL, and CONFIG_SHA_PROG_HW_ACCEL. However, no defconfig has migrated to it. Complete the move by first adding additional logic to various Kconfig files to select this when required and then use the moveconfig tool. In many cases we can select these because they are required to implement other drivers. We also correct how we include the various hashing algorithms in SPL. This commit was generated as follows (after Kconfig additions): [1] tools/moveconfig.py -y SHA1 SHA256 SHA_HW_ACCEL [2] tools/moveconfig.py -y SHA_PROG_HW_ACCEL Note: We cannot move SHA_HW_ACCEL and SHA_PROG_HW_ACCEL simultaneously because there is dependency between them. Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com> Cc: Naveen Burmi <NaveenBurmi@freescale.com> Cc: Po Liu <po.liu@freescale.com> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Priyanka Jain <Priyanka.Jain@freescale.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Chander Kashyap <k.chander@samsung.com> Cc: Steve Rae <steve.rae@raedomain.com> Cc: Dirk Eibach <eibach@gdsys.de> Cc: Feng Li <feng.li_2@nxp.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Sumit Garg <sumit.garg@nxp.com> Cc: Mingkai Hu <Mingkai.Hu@freescale.com> Cc: York Sun <york.sun@nxp.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Akshay Saraswat <akshay.s@samsung.com> Cc: Heiko Schocher <hs@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
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c04b9b34 |
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26-Apr-2017 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_CMD_BLOB to Kconfig This converts the following to Kconfig: CONFIG_CMD_BLOB Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Add imply CMD_BLOB under CHAIN_OF_TRUST] Signed-off-by: Tom Rini <trini@konsulko.com> |
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0645c23a |
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30-Mar-2017 |
VINITHA PILLAI <vinitha.pillai@nxp.com> |
powerpc: T1042RDB: SECURE BOOT: Remove CONFIG_CMD_BLOB from SPL compilation BLOB feature is not required during SPL compilation. Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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28522678 |
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01-Mar-2017 |
Tom Rini <trini@konsulko.com> |
Freescale/NXP: Migrate CONFIG_FSL_CAAM to defconfigs In some cases this is absolutely required, so select this for some secure features. This also requires migration of RSA_FREESCALE_EXP Cc: Ruchika Gupta <ruchika.gupta@nxp.com> Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com> Cc: Naveen Burmi <NaveenBurmi@freescale.com> Cc: Po Liu <po.liu@freescale.com> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Priyanka Jain <Priyanka.Jain@freescale.com> Cc: Sumit Garg <sumit.garg@nxp.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Feng Li <feng.li_2@nxp.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Mingkai Hu <Mingkai.Hu@freescale.com> Cc: York Sun <york.sun@nxp.com> Cc: Saksham Jain <saksham.jain@nxp.freescale.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
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88077715 |
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22-Jan-2017 |
Tom Rini <trini@konsulko.com> |
NXP: Introduce board/freescale/common/Kconfig and migrate CHAIN_OF_TRUST Introduce board/freescale/common/Kconfig so that we have a single place for CONFIG options that are shared between ARM and PowerPC NXP platforms. Cc: York Sun <york.sun@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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3788b451 |
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21-Jan-2017 |
Jagan Teki <jagan@openedev.com> |
config: Move CONFIG_BOARD_LATE_INIT to defconfigs Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jagan@openedev.com> |
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a1055038 |
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28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T104xQDS: Remove macro CONFIG_T104xD4QDS Remove this macro. It was added by e622d9ed but actually wasn't used. Signed-off-by: York Sun <york.sun@nxp.com> |
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86e0a313 |
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28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T2080RDB: Remove macro CONFIG_T2080RDB Use TARGET_T2080RDB from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com> |
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80d26188 |
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28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T2080QDS: Remove macro T2080QDS Use TARGET_T2080QDS from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com> |
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f4f66940 |
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28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1040QDS: Remove macro CONFIG_T1040QDS Use TARGET_T1040QDS from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com> |
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673c01c7 |
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21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4240QDS: Remove macro CONFIG_T4240QDS Use CONFIG_TARGET_T4240QDS instead. Signed-off-by: York Sun <york.sun@nxp.com> |
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9c21d06c |
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21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4160QDS: Separate from T4240QDS in Kconfig Use TARGET_T4160QDS to simplify Kconfig options. Signed-off-by: York Sun <york.sun@nxp.com> |
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78e56995 |
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21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T104xRDB: Remove macro CONFIG_T104xRDB and T104xD4RDB CONFIG_T104xRDB is defined in T104xRDB.h, so it is always enabled for all T1040RDB, T1040D4RDB, T1042RDB, T1042D4RDB, T1042RDB_PI. CONFIG_T104XD4RDB is defined for all T1040D4RDB, T1042D4RDB. Signed-off-by: York Sun <york.sun@nxp.com> |
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e5d5f5a8 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1024: Remove macro CONFIG_PPC_T1024 Replace CONFIG_PPC_T1024 with ARCH_T1024 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
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5ff3f41d |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1023: Remove macro CONFIG_PPC_T1023 Replace CONFIG_PPC_T1023 with ARCH_T1023 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
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d46a4a13 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: B4860QDS: Remove macro CONFIG_B4860QDS Use CONFIG_TARGET_B4860QDS instead. Signed-off-by: York Sun <york.sun@nxp.com> |
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95390360 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P5040: Remove macro CONFIG_P5040 Replace CONFIG_P5040 with ARCH_P5040 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
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cefe11cd |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P5020: Remove macro CONFIG_PPC_P5020 Replace CONFIG_PPC_P5020 with ARCH_P5020 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
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e71372cb |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P4080: Remove macro CONFIG_PPC_P4080 Replace CONFIG_PPC_P4080 with ARCH_P4080 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
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5e5fdd2d |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P3041: Remove macro CONFIG_PPC_P3041 Replace CONFIG_PPC_P3041 with ARCH_P3041 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
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ce040c83 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P2041: Remove macro CONFIG_PPC_P2041 Replace CONFIG_PPC_P2041 with ARCH_P2041 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
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ebccf255 |
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16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: C29XPCIE: Remove macro CONFIG_C29XPCIE Use CONFIG_TARGET_C29XPCIE instead. Signed-off-by: York Sun <york.sun@nxp.com> |
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a202b9f8 |
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15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: BSC9132QDS: Remove CONFIG_BSC9132QDS macro Use CONFIG_TARGET_BSC9132QDS from Kconfig option, remove CONFIG_BSC9132QDS macro. Signed-off-by: York Sun <york.sun@nxp.com> |
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d3662dff |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_SPL_DRIVERS_MISC_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org> |
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d3e7e2b2 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_SPL_HASH_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org> |
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dbdaeee4 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_SPL_CRYPTO_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org> |
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d3c1f467 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Move existing use of CONFIG_SPL_RSA to Kconfig A few boards define this in a header file which is incorrect. It means that Kconfig options that rely on this cannot be used. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> |
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3433a693 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Move existing use of CONFIG_SPL_DM to Kconfig A few boards define this in a header file which is incorrect. It means that Kconfig options that rely on this cannot be used. Move it. Note that quite a few boards defined this options but do not appear to actually use SPL: BSC9132QDS_NOR_DDRCLK100_SECURE BSC9132QDS_NOR_DDRCLK133_SECURE BSC9132QDS_SDCARD_DDRCLK100_SECURE BSC9132QDS_SDCARD_DDRCLK133_SECURE BSC9132QDS_SPIFLASH_DDRCLK100_SECURE BSC9132QDS_SPIFLASH_DDRCLK133_SECURE C29XPCIE_NOR_SECBOOT P1010RDB-PA_36BIT_NAND_SECBOOT P1010RDB-PA_36BIT_SPIFLASH_SECBOOT P1010RDB-PA_NAND_SECBOOT P1010RDB-PA_NOR_SECBOOT P1010RDB-PB_36BIT_NOR_SECBOOT P1010RDB-PB_36BIT_SPIFLASH_SECBOOT P1010RDB-PB_NAND_SECBOOT P1010RDB-PB_NOR_SECBOOT P3041DS_SECURE_BOOT P4080DS_SECURE_BOOT P5020DS_NAND_SECURE_BOOT P5040DS_SECURE_BOOT T1023RDB_SECURE_BOOT T1024QDS_DDR4_SECURE_BOOT T1024QDS_SECURE_BOOT T1024RDB_SECURE_BOOT T1040RDB_SECURE_BOOT T1042D4RDB_SECURE_BOOT T1042RDB_SECURE_BOOT T2080QDS_SECURE_BOOT T2080RDB_SECURE_BOOT T4160QDS_SECURE_BOOT T4240QDS_SECURE_BOOT ls1021aqds_nor_SECURE_BOOT ls1021atwr_nor_SECURE_BOOT ls1043ardb_SECURE_BOOT For these boards CONFIG_SPL_DM will no-longer be defined in SPL. But since they apparently don't have an SPL, this should not matter. Signed-off-by: Simon Glass <sjg@chromium.org> |
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b63f8a43 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
arm: fsl: Adjust ordering of #ifndef CONFIG_SPL_BUILD The secure boot header files incorrectly define SPL options only if CONFIG_SPL_BUILD is defined. This means that the options are only enabled in an SPL build, and not with a normal 'make xxx_defconfig'. This means that moveconfig.py cannot work, since it sees the options as disabled even when they may be manually enabled in an SPL build. Fix this by changing the order. Signed-off-by: Simon Glass <sjg@chromium.org> |
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69d4b48c |
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14-Jun-2016 |
Sumit Garg <sumit.garg@nxp.com> |
SECURE_BOOT: Enable SD as a source for bootscript Add support for reading bootscript and bootscript header from SD. Also renamed macros *_FLASH to *_DEVICE to represent SD alongwith NAND and NOR flash. Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
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aa36c84e |
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13-Jul-2016 |
Sumit Garg <sumit.garg@nxp.com> |
powerpc/mpc85xx: T104x: Add nand secure boot target For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In non-secure boot scenario from NAND, this address will map to CPC configured as SRAM. But in case of secure boot, this default address always maps to IBR (Internal Boot ROM). The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. For secure boot target from NAND, the text base for SPL is kept same as non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000) As a the virtual and physical address of CPC would be different. The virtual address 0xFFFx_xxxx needs to be mapped to physical address 0xBFFx_xxxx. Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000 and update DCFG SCRTACH1 register with location of Header required for secure boot. The changes are similar to commit 467a40dfe35f48d830f01a72617207d03ca85b4d powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC is only 256K and thus SPL framework is used. The changes are only applicable for SPL U-Boot running out of CPC SRAM and not the next level U-Boot loaded on DDR. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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8f01397b |
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13-Jul-2016 |
Sumit Garg <sumit.garg@nxp.com> |
powerpc/mpc85xx: SECURE BOOT- Enable chain of trust in SPL As part of Chain of Trust for Secure boot, the SPL U-Boot will validate the next level U-boot image. Add a new function spl_validate_uboot to perform the validation. Enable hardware crypto operations in SPL using SEC block. In case of Secure Boot, PAMU is not bypassed. For allowing SEC block access to CPC configured as SRAM, configure PAMU. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
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73223f0e |
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22-Feb-2016 |
Simon Glass <sjg@chromium.org> |
Kconfig: Move CONFIG_FIT and related options to Kconfig There are already two FIT options in Kconfig but the CONFIG options are still in the header files. We need to do a proper move to fix this. Move these options to Kconfig and tidy up board configuration: CONFIG_FIT CONFIG_OF_BOARD_SETUP CONFIG_OF_SYSTEM_SETUP CONFIG_FIT_SIGNATURE CONFIG_FIT_BEST_MATCH CONFIG_FIT_VERBOSE CONFIG_OF_STDOUT_VIA_ALIAS CONFIG_RSA Unfortunately the first one is a little complicated. We need to make sure this option is not enabled in SPL by this change. Also this option is enabled automatically in the host builds by defining CONFIG_FIT in the image.h file. To solve this, add a new IMAGE_USE_FIT #define which can be used in files that are built on the host but must also build for U-Boot and SPL. Note: Masahiro's moveconfig.py script is amazing. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Add microblaze change, various configs/ re-applies] Signed-off-by: Tom Rini <trini@konsulko.com> |
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9e971632 |
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22-Feb-2016 |
Simon Glass <sjg@chromium.org> |
freescale: Remove CONFIG_DM from header files Kconfig options must defined in the defconfig files. Since RSA_SOFTWARE_EXP relies on CONFIG_DM, unless it is set in kconfig we cannot enable RSA. Remove the hacks which enable CONFIG_DM in header files and update the defconfig. Signed-off-by: Simon Glass <sjg@chromium.org> |
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d0a6d7ce |
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22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: enable chain of trust for PowerPC platforms Chain of Trust is enabled for PowerPC platforms for Secure Boot. CONFIG_BOARD_LATE_INIT is defined. In board_late_init(), fsl_setenv_chain_of_trust() is called which will perform the following: - If boot mode is non-secure, return (No Change) - If boot mode is secure, set the following environmet variables: bootdelay = 0 (To disable Boot Prompt) bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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bdc22074 |
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22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: split the secure boot functionality in two parts There are two phases in Secure Boot 1. ISBC: In BootROM, validate the BootLoader (U-Boot). 2. ESBC: In U-Boot, continuing the Chain of Trust by validating and booting LINUX. For ESBC phase, there is no difference in SoC's based on ARM or PowerPC cores. But the exit conditions after ISBC phase i.e. entry conditions for U-Boot are different for ARM and PowerPC. PowerPC: If Secure Boot is executed, a separate U-Boot target is required which must be compiled with a diffrent Text Base as compared to Non-Secure Boot. There are some LAW and TLB settings which are required specifically for Secure Boot scenario. ARM: ARM based SoC's have a fixed memory map and exit conditions from BootROM are same irrespective of boot mode (Secure or Non-Secure). Thus the current Secure Boot functionlity has been split into two parts: CONFIG_CHAIN_OF_TRUST This will have the following functionality as part of U-Boot: 1. Enable commands like esbc_validate, esbc_halt 2. Change the environment settings based on bootmode, determined at run time: - If bootmode is non-secure, no change - If bootmode is secure, set the following: - bootdelay = 0 (Don't give boot prompt) - bootcmd = Validate and execute the bootscript. CONFIG_SECURE_BOOT This is defined only for creating a different compile time target for secure boot. Traditionally, both these functionalities were defined under CONFIG_SECURE_BOOT. This patch is aimed at removing the requirement for a separate Secure Boot target for ARM based SoC's. CONFIG_CHAIN_OF_TRUST will be defined and boot mode will be determine at run time. Another Security Requirement for running CHAIN_OF_TRUST is that U-Boot environemnt must not be picked from flash/external memory. This cannot be done based on bootmode at run time in current U-Boot architecture. Once this dependency is resolved, no separate SECURE_BOOT target will be required for ARM based SoC's. Currently, the only code under CONFIG_SECURE_BOOT for ARM SoC's is defining CONFIG_ENV_IS_NOWHERE Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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74eecd82 |
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22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: include/configs: move definition of CONFIG_CMD_BLOB CONFIG_CMD_BLOB must be defined in case of Secure Boot. It was earlier defined in all config files. The definition has been moved to a common file which is included by all configs. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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2ed948f4 |
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31-Jul-2015 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
SECURE_BOOT: Disable IE Key feature for RAMBOOT ISBC Key Extension feature is not applicable for RAMBOOT as there is no way to retrieve the CSF Header and validated IE Key table from SRAM once CPC has been disabled. The feature is only applicable in case of NOR SECURE BOOT. Code Cleanup: The SECURE_BOOT specific defines have been moved from arch-ls102xa/config.h to arm/include/asm/fsl_secure_boot.h Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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5050f6f0 |
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15-Jun-2015 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT-Copy Boot Script on RAM For running Chain of Trust when doing Secure Boot from NAND, the Bootscript header and bootscript must be copied from NAND to RAM(DDR). The addresses and commands for the same have been defined. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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467a40df |
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15-Jun-2015 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 Secure Boot Target is added for NAND for P3041. For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In case of secure boot, this default address maps to Boot ROM. The Boot ROM code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is configured as SRAM. U-Boot binary will be located on SRAM configured at address 0xBFF00000. In the U-Boot code, TLB entries are created to map the virtual address 0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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e622d9ed |
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26-Mar-2015 |
gaurav rana <gaurav.rana@freescale.com> |
powerpc/T104xD4: Add Secure boot support for T104xD4RDB platforms defconfig files are added and SFP version for these platforms is updated. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
98cb0efd |
|
10-Mar-2015 |
gaurav rana <gaurav.rana@freescale.com> |
Add bootscript support to esbc_validate. 1. Default environment will be used for secure boot flow which can't be edited or saved. 2. Command for secure boot is predefined in the default environment which will run on autoboot (and autoboot is the only option allowed in case of secure boot) and it looks like this: #define CONFIG_SECBOOT \ "setenv bs_hdraddr 0xe8e00000;" \ "esbc_validate $bs_hdraddr;" \ "source $img_addr;" \ "esbc_halt;" #endif 3. Boot Script can contain esbc_validate commands and bootm command. Uboot source command used in default secure boot command will run the bootscript. 4. Command esbc_halt added to ensure either bootm executes after validation of images or core should just spin. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e04916a7 |
|
26-Feb-2015 |
gaurav rana <gaurav.rana@freescale.com> |
SECURE_BOOT : enable esbc_validate command for powerpc and arm platforms. esbc_validate command uses various IP Blocks: Security Monitor, CAAM block and SFP registers. Hence the respective CONFIG's are enabled. Apart from these CONFIG_SHA_PROG_HW_ACCEL and CONFIG_RSA are also enabled. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
b3f0f632 |
|
12-Dec-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: Define PBI Flash Base for C29XPCIE Secure Boot CONFIG_SYS_PBI_FLASH_BASE is defined for Secure Boot on C29X Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
f6050790 |
|
24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/mpc85xx: Add T1024/T1023 SoC support Add support for Freescale T1024/T1023 SoC. The T1024 SoC includes the following function and features: - Two 64-bit Power architecture e5500 cores, up to 1.4GHz - private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC) - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration - Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI) - High-speed peripheral interfaces - Three PCI Express 2.0 controllers - Additional peripheral interfaces - One SATA 2.0 controller - Two USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/eSDHC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Two 8-channel DMA engines - Multicore programmable interrupt controller (PIC) - LCD interface (DIU) with 12 bit dual data rate - QUICC Engine block supporting TDM, HDLC, and UART - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T1024 and T1023: Feature T1024 T1023 QUICC Engine: yes no DIU: yes no Deep Sleep: yes no I2C controller: 4 3 DDR: 64-bit 32-bit IFC: 32-bit 28-bit Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e47c2a68 |
|
22-Apr-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080RDB Secure Boot Target is added for T2080RDB Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080RDB. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> |
#
40678159 |
|
22-Apr-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- secure boot target for t1040rdb T1040RDB.h file is removed and a unified file T104xRDB.h is created. Hence macro CONFIG_T1040 is renamed to CONFIG_T104x. Signed-off-by: Gaurav Kumar Rana <gaurav.rana@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> |
#
2d8db6d3 |
|
18-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T1040QDS and T1040RDB Secure Boot Target is added for T1040QDS and T1040RDB Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T1040QDS and CONFIG_T1040RDB Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
ca4819df |
|
18-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080QDS Secure Boot Target is added for T2080QDS Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080QDS. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
796a7810 |
|
18-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T4240QDS and T4160QDS Secure Boot Target is added for T4240QDS and T4160QDS Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T4240QDS. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
fb4a2409 |
|
18-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS Changes: 1. L2 cache is being invalidated by Boot ROM code for e6500 core. So removing the invalidation from start.S 2. Clear the LAW and corresponding configuration for CPC. Boot ROM code uses it as hosekeeping area. 3. For Secure boot, CPC is configured as SRAM and used as house keeping area. This configuration is to be disabled once in uboot. Earlier this disabling of CPC as SRAM was happening in cpu_init_r. As a result cache invalidation function was getting skipped in case CPC is configured as SRAM.This was causing random crashes. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
f978f7c2 |
|
11-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for BSC9132QDS Add NOR, SPI and SD secure boot targets for BSC9132QDS. Changes: - Debug TLB entry is not required for Secure Boot Target. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
0d2cff2d |
|
21-Aug-2013 |
Po Liu <po.liu@freescale.com> |
powerpc: add CONFIG_SECURE_BOOT condition into fsl_secure_boot.h This patch is for board config file not to add CONFIG_SECURE_BOOT condition for include the asm/fsl_secure_boot.h. Signed-off-by: Po Liu <Po.Liu@freescale.com> |
#
1a459660 |
|
08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
39bdaff4 |
|
25-Mar-2013 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
SECURE BOOT - Removed deletion of TLB entries code Boot ROM code creates TLB entries for 3.5G space before entering the u-boot. Earlier we were deleting these entries after early initialization of CPU. In recent past, code has been added to invalidate all these entries before relocation of u-boot code. So this code to delete TLB entries after CPU initialization is no longer required. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Acked-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
7065b7d4 |
|
15-Dec-2010 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
powerpc/p4080: Add support for secure boot flow Pre u-boot Flow: 1. User loads the u-boot image in flash 2. PBL/Configuration word is used to create LAW for Flash at 0xc0000000 (Please note that ISBC expects all these addresses, images to be validated, entry point etc within 0 - 3.5G range) 3. ISBC validates the u-boot image, and passes control to u-boot at 0xcffffffc. Changes in u-boot: 1. Temporarily map CONFIG_SYS_MONITOR_BASE to the 1M CONFIG_SYS_PBI_FLASH_WINDOW in AS=1. (The CONFIG_SYS_PBI_FLASH_WINDOW is the address map for the flash created by PBL/configuration word within 0 - 3.5G memory range. The u-boot image at this address has been validated by ISBC code) 2. Remove TLB entries for 0 - 3.5G created by ISBC code 3. Remove the LAW entry for the CONFIG_SYS_PBI_FLASH_WINDOW created by PBL/configuration word after switch to AS = 1 Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com> Acked-by: Wood Scott-B07421 <B07421@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
f6c1f917 |
|
25-Jun-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_SYS_FSL_CPC et al to Kconfig This converts the following to Kconfig: CONFIG_SYS_FSL_CPC CONFIG_SYS_CPC_REINIT_F Signed-off-by: Tom Rini <trini@konsulko.com> |
#
f4cd75e9 |
|
17-Jun-2022 |
Tom Rini <trini@konsulko.com> |
powerpc: Clean up CHAIN_OF_TRUST related options As things stand currently, there is only one PowerPC platform that enables the options for CHAIN_OF_TRUST. From the board header files, remove a number of never-set options. Remove board specific values from arch/powerpc/include/asm/fsl_secure_boot.h as well. Rework include/config_fsl_chain_trust.h to not abuse the CONFIG namespace for constructing CHAIN_BOOT_CMD. Migrate all of the configurable addresses to Kconfig. If any platforms are re-introduced with secure boot support, everything required should still be here, but now in Kconfig, or requires migration of an option to Kconfig. Cc: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5aad0a14 |
|
17-Jun-2022 |
Tom Rini <trini@konsulko.com> |
fsl_validate: Migrate SPL_UBOOT_KEY_HASH to Kconfig Move setting of SPL_UBOOT_KEY_HASH to a non-NULL value to Kconfig. As part of this, change fsl_secboot_validate(...) to check that it is passed a non-empty string, rather than non-NULL. Cc: Peng Fan <peng.fan@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Kshitiz Varshney <kshitiz.varshney@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
601483ff |
|
16-Jun-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_SYS_FSL_SFP_BE et al to Kconfig This converts the following to Kconfig: CONFIG_KEY_REVOCATION CONFIG_SYS_FSL_SFP_BE CONFIG_SYS_FSL_SFP_LE CONFIG_SYS_FSL_SFP_VER_3_0 CONFIG_SYS_FSL_SFP_VER_3_2 CONFIG_SYS_FSL_SFP_VER_3_4 CONFIG_SYS_FSL_SRK_LE This partly means making sure to enable SYS_FSL_ERRATUM_A007186 only for when CHAIN_OF_TRUST is enabled. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
c9f85187 |
|
16-Jun-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_SYS_FSL_SEC_MON et al to Kconfig This converts the following to Kconfig: CONFIG_SYS_FSL_SEC_MON CONFIG_SYS_FSL_SEC_MON_BE CONFIG_SYS_FSL_SEC_MON_LE Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ec6b37ce |
|
23-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove T4160RDB board This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it. As this is the last ARCH_T4160 platform, remove that support as well. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
6c3d9933 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove T1023RBD boards and T1024RDB_SECURE_BOOT These boards have not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove them. As this is the only ARCH_T1023 platform left, remove that support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
008e9965 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove many T104x boards These boards have not been converted to CONFIG_DM_PCI, CONFIG_DM_USB or in some cases CONFIG_DM itself by the deadline. Remove them. Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a99dab1d |
|
20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove Cyrus_P5020 and P5040 boards These boards have not been converted to CONFIG_DM_MMC by the deadline. Remove them. As the P5020 is the last ARCH_P5020 platform, remove that support as well. Cc: Andy Fleming <afleming@gmail.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
bf85995a |
|
20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove TARGET_T1040QDS references The TARGET_T1040QDS platforms have been removed already, drop some remaining references in the code. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
bef18454 |
|
07-Nov-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
freescale/powerpc: Rename the config CONFIG_SECURE_BOOT name Rename the CONFIG_SECURE_BOOT name to CONFIG_NXP_ESBC to avoid conflicts with UEFI secure boot. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ea7971f7 |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_CMD_ESBC_VALIDATE to Kconfig This converts the following to Kconfig: CONFIG_CMD_ESBC_VALIDATE Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
089df18b |
|
14-May-2017 |
Tom Rini <trini@konsulko.com> |
lib: move hash CONFIG options to Kconfig Commit 94e3c8c4fd7b ("crypto/fsl - Add progressive hashing support using hardware acceleration.") created entries for CONFIG_SHA1, CONFIG_SHA256, CONFIG_SHA_HW_ACCEL, and CONFIG_SHA_PROG_HW_ACCEL. However, no defconfig has migrated to it. Complete the move by first adding additional logic to various Kconfig files to select this when required and then use the moveconfig tool. In many cases we can select these because they are required to implement other drivers. We also correct how we include the various hashing algorithms in SPL. This commit was generated as follows (after Kconfig additions): [1] tools/moveconfig.py -y SHA1 SHA256 SHA_HW_ACCEL [2] tools/moveconfig.py -y SHA_PROG_HW_ACCEL Note: We cannot move SHA_HW_ACCEL and SHA_PROG_HW_ACCEL simultaneously because there is dependency between them. Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com> Cc: Naveen Burmi <NaveenBurmi@freescale.com> Cc: Po Liu <po.liu@freescale.com> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Priyanka Jain <Priyanka.Jain@freescale.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Chander Kashyap <k.chander@samsung.com> Cc: Steve Rae <steve.rae@raedomain.com> Cc: Dirk Eibach <eibach@gdsys.de> Cc: Feng Li <feng.li_2@nxp.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Sumit Garg <sumit.garg@nxp.com> Cc: Mingkai Hu <Mingkai.Hu@freescale.com> Cc: York Sun <york.sun@nxp.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Akshay Saraswat <akshay.s@samsung.com> Cc: Heiko Schocher <hs@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
c04b9b34 |
|
26-Apr-2017 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_CMD_BLOB to Kconfig This converts the following to Kconfig: CONFIG_CMD_BLOB Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Add imply CMD_BLOB under CHAIN_OF_TRUST] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
0645c23a |
|
30-Mar-2017 |
VINITHA PILLAI <vinitha.pillai@nxp.com> |
powerpc: T1042RDB: SECURE BOOT: Remove CONFIG_CMD_BLOB from SPL compilation BLOB feature is not required during SPL compilation. Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
28522678 |
|
01-Mar-2017 |
Tom Rini <trini@konsulko.com> |
Freescale/NXP: Migrate CONFIG_FSL_CAAM to defconfigs In some cases this is absolutely required, so select this for some secure features. This also requires migration of RSA_FREESCALE_EXP Cc: Ruchika Gupta <ruchika.gupta@nxp.com> Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com> Cc: Naveen Burmi <NaveenBurmi@freescale.com> Cc: Po Liu <po.liu@freescale.com> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Priyanka Jain <Priyanka.Jain@freescale.com> Cc: Sumit Garg <sumit.garg@nxp.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Feng Li <feng.li_2@nxp.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Mingkai Hu <Mingkai.Hu@freescale.com> Cc: York Sun <york.sun@nxp.com> Cc: Saksham Jain <saksham.jain@nxp.freescale.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
88077715 |
|
22-Jan-2017 |
Tom Rini <trini@konsulko.com> |
NXP: Introduce board/freescale/common/Kconfig and migrate CHAIN_OF_TRUST Introduce board/freescale/common/Kconfig so that we have a single place for CONFIG options that are shared between ARM and PowerPC NXP platforms. Cc: York Sun <york.sun@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3788b451 |
|
21-Jan-2017 |
Jagan Teki <jagan@openedev.com> |
config: Move CONFIG_BOARD_LATE_INIT to defconfigs Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jagan@openedev.com> |
#
a1055038 |
|
28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T104xQDS: Remove macro CONFIG_T104xD4QDS Remove this macro. It was added by e622d9ed but actually wasn't used. Signed-off-by: York Sun <york.sun@nxp.com> |
#
86e0a313 |
|
28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T2080RDB: Remove macro CONFIG_T2080RDB Use TARGET_T2080RDB from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
80d26188 |
|
28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T2080QDS: Remove macro T2080QDS Use TARGET_T2080QDS from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
f4f66940 |
|
28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1040QDS: Remove macro CONFIG_T1040QDS Use TARGET_T1040QDS from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
673c01c7 |
|
21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4240QDS: Remove macro CONFIG_T4240QDS Use CONFIG_TARGET_T4240QDS instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9c21d06c |
|
21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4160QDS: Separate from T4240QDS in Kconfig Use TARGET_T4160QDS to simplify Kconfig options. Signed-off-by: York Sun <york.sun@nxp.com> |
#
78e56995 |
|
21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T104xRDB: Remove macro CONFIG_T104xRDB and T104xD4RDB CONFIG_T104xRDB is defined in T104xRDB.h, so it is always enabled for all T1040RDB, T1040D4RDB, T1042RDB, T1042D4RDB, T1042RDB_PI. CONFIG_T104XD4RDB is defined for all T1040D4RDB, T1042D4RDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e5d5f5a8 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1024: Remove macro CONFIG_PPC_T1024 Replace CONFIG_PPC_T1024 with ARCH_T1024 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5ff3f41d |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1023: Remove macro CONFIG_PPC_T1023 Replace CONFIG_PPC_T1023 with ARCH_T1023 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
d46a4a13 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: B4860QDS: Remove macro CONFIG_B4860QDS Use CONFIG_TARGET_B4860QDS instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
95390360 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P5040: Remove macro CONFIG_P5040 Replace CONFIG_P5040 with ARCH_P5040 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
cefe11cd |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P5020: Remove macro CONFIG_PPC_P5020 Replace CONFIG_PPC_P5020 with ARCH_P5020 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e71372cb |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P4080: Remove macro CONFIG_PPC_P4080 Replace CONFIG_PPC_P4080 with ARCH_P4080 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5e5fdd2d |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P3041: Remove macro CONFIG_PPC_P3041 Replace CONFIG_PPC_P3041 with ARCH_P3041 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ce040c83 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P2041: Remove macro CONFIG_PPC_P2041 Replace CONFIG_PPC_P2041 with ARCH_P2041 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ebccf255 |
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16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: C29XPCIE: Remove macro CONFIG_C29XPCIE Use CONFIG_TARGET_C29XPCIE instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a202b9f8 |
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15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: BSC9132QDS: Remove CONFIG_BSC9132QDS macro Use CONFIG_TARGET_BSC9132QDS from Kconfig option, remove CONFIG_BSC9132QDS macro. Signed-off-by: York Sun <york.sun@nxp.com> |
#
d3662dff |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_SPL_DRIVERS_MISC_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d3e7e2b2 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_SPL_HASH_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
dbdaeee4 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_SPL_CRYPTO_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d3c1f467 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Move existing use of CONFIG_SPL_RSA to Kconfig A few boards define this in a header file which is incorrect. It means that Kconfig options that rely on this cannot be used. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3433a693 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Move existing use of CONFIG_SPL_DM to Kconfig A few boards define this in a header file which is incorrect. It means that Kconfig options that rely on this cannot be used. Move it. Note that quite a few boards defined this options but do not appear to actually use SPL: BSC9132QDS_NOR_DDRCLK100_SECURE BSC9132QDS_NOR_DDRCLK133_SECURE BSC9132QDS_SDCARD_DDRCLK100_SECURE BSC9132QDS_SDCARD_DDRCLK133_SECURE BSC9132QDS_SPIFLASH_DDRCLK100_SECURE BSC9132QDS_SPIFLASH_DDRCLK133_SECURE C29XPCIE_NOR_SECBOOT P1010RDB-PA_36BIT_NAND_SECBOOT P1010RDB-PA_36BIT_SPIFLASH_SECBOOT P1010RDB-PA_NAND_SECBOOT P1010RDB-PA_NOR_SECBOOT P1010RDB-PB_36BIT_NOR_SECBOOT P1010RDB-PB_36BIT_SPIFLASH_SECBOOT P1010RDB-PB_NAND_SECBOOT P1010RDB-PB_NOR_SECBOOT P3041DS_SECURE_BOOT P4080DS_SECURE_BOOT P5020DS_NAND_SECURE_BOOT P5040DS_SECURE_BOOT T1023RDB_SECURE_BOOT T1024QDS_DDR4_SECURE_BOOT T1024QDS_SECURE_BOOT T1024RDB_SECURE_BOOT T1040RDB_SECURE_BOOT T1042D4RDB_SECURE_BOOT T1042RDB_SECURE_BOOT T2080QDS_SECURE_BOOT T2080RDB_SECURE_BOOT T4160QDS_SECURE_BOOT T4240QDS_SECURE_BOOT ls1021aqds_nor_SECURE_BOOT ls1021atwr_nor_SECURE_BOOT ls1043ardb_SECURE_BOOT For these boards CONFIG_SPL_DM will no-longer be defined in SPL. But since they apparently don't have an SPL, this should not matter. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
b63f8a43 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
arm: fsl: Adjust ordering of #ifndef CONFIG_SPL_BUILD The secure boot header files incorrectly define SPL options only if CONFIG_SPL_BUILD is defined. This means that the options are only enabled in an SPL build, and not with a normal 'make xxx_defconfig'. This means that moveconfig.py cannot work, since it sees the options as disabled even when they may be manually enabled in an SPL build. Fix this by changing the order. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
69d4b48c |
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14-Jun-2016 |
Sumit Garg <sumit.garg@nxp.com> |
SECURE_BOOT: Enable SD as a source for bootscript Add support for reading bootscript and bootscript header from SD. Also renamed macros *_FLASH to *_DEVICE to represent SD alongwith NAND and NOR flash. Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
aa36c84e |
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13-Jul-2016 |
Sumit Garg <sumit.garg@nxp.com> |
powerpc/mpc85xx: T104x: Add nand secure boot target For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In non-secure boot scenario from NAND, this address will map to CPC configured as SRAM. But in case of secure boot, this default address always maps to IBR (Internal Boot ROM). The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. For secure boot target from NAND, the text base for SPL is kept same as non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000) As a the virtual and physical address of CPC would be different. The virtual address 0xFFFx_xxxx needs to be mapped to physical address 0xBFFx_xxxx. Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000 and update DCFG SCRTACH1 register with location of Header required for secure boot. The changes are similar to commit 467a40dfe35f48d830f01a72617207d03ca85b4d powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC is only 256K and thus SPL framework is used. The changes are only applicable for SPL U-Boot running out of CPC SRAM and not the next level U-Boot loaded on DDR. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
8f01397b |
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13-Jul-2016 |
Sumit Garg <sumit.garg@nxp.com> |
powerpc/mpc85xx: SECURE BOOT- Enable chain of trust in SPL As part of Chain of Trust for Secure boot, the SPL U-Boot will validate the next level U-boot image. Add a new function spl_validate_uboot to perform the validation. Enable hardware crypto operations in SPL using SEC block. In case of Secure Boot, PAMU is not bypassed. For allowing SEC block access to CPC configured as SRAM, configure PAMU. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
73223f0e |
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22-Feb-2016 |
Simon Glass <sjg@chromium.org> |
Kconfig: Move CONFIG_FIT and related options to Kconfig There are already two FIT options in Kconfig but the CONFIG options are still in the header files. We need to do a proper move to fix this. Move these options to Kconfig and tidy up board configuration: CONFIG_FIT CONFIG_OF_BOARD_SETUP CONFIG_OF_SYSTEM_SETUP CONFIG_FIT_SIGNATURE CONFIG_FIT_BEST_MATCH CONFIG_FIT_VERBOSE CONFIG_OF_STDOUT_VIA_ALIAS CONFIG_RSA Unfortunately the first one is a little complicated. We need to make sure this option is not enabled in SPL by this change. Also this option is enabled automatically in the host builds by defining CONFIG_FIT in the image.h file. To solve this, add a new IMAGE_USE_FIT #define which can be used in files that are built on the host but must also build for U-Boot and SPL. Note: Masahiro's moveconfig.py script is amazing. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Add microblaze change, various configs/ re-applies] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
9e971632 |
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22-Feb-2016 |
Simon Glass <sjg@chromium.org> |
freescale: Remove CONFIG_DM from header files Kconfig options must defined in the defconfig files. Since RSA_SOFTWARE_EXP relies on CONFIG_DM, unless it is set in kconfig we cannot enable RSA. Remove the hacks which enable CONFIG_DM in header files and update the defconfig. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d0a6d7ce |
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22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: enable chain of trust for PowerPC platforms Chain of Trust is enabled for PowerPC platforms for Secure Boot. CONFIG_BOARD_LATE_INIT is defined. In board_late_init(), fsl_setenv_chain_of_trust() is called which will perform the following: - If boot mode is non-secure, return (No Change) - If boot mode is secure, set the following environmet variables: bootdelay = 0 (To disable Boot Prompt) bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
bdc22074 |
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22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: split the secure boot functionality in two parts There are two phases in Secure Boot 1. ISBC: In BootROM, validate the BootLoader (U-Boot). 2. ESBC: In U-Boot, continuing the Chain of Trust by validating and booting LINUX. For ESBC phase, there is no difference in SoC's based on ARM or PowerPC cores. But the exit conditions after ISBC phase i.e. entry conditions for U-Boot are different for ARM and PowerPC. PowerPC: If Secure Boot is executed, a separate U-Boot target is required which must be compiled with a diffrent Text Base as compared to Non-Secure Boot. There are some LAW and TLB settings which are required specifically for Secure Boot scenario. ARM: ARM based SoC's have a fixed memory map and exit conditions from BootROM are same irrespective of boot mode (Secure or Non-Secure). Thus the current Secure Boot functionlity has been split into two parts: CONFIG_CHAIN_OF_TRUST This will have the following functionality as part of U-Boot: 1. Enable commands like esbc_validate, esbc_halt 2. Change the environment settings based on bootmode, determined at run time: - If bootmode is non-secure, no change - If bootmode is secure, set the following: - bootdelay = 0 (Don't give boot prompt) - bootcmd = Validate and execute the bootscript. CONFIG_SECURE_BOOT This is defined only for creating a different compile time target for secure boot. Traditionally, both these functionalities were defined under CONFIG_SECURE_BOOT. This patch is aimed at removing the requirement for a separate Secure Boot target for ARM based SoC's. CONFIG_CHAIN_OF_TRUST will be defined and boot mode will be determine at run time. Another Security Requirement for running CHAIN_OF_TRUST is that U-Boot environemnt must not be picked from flash/external memory. This cannot be done based on bootmode at run time in current U-Boot architecture. Once this dependency is resolved, no separate SECURE_BOOT target will be required for ARM based SoC's. Currently, the only code under CONFIG_SECURE_BOOT for ARM SoC's is defining CONFIG_ENV_IS_NOWHERE Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
74eecd82 |
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22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: include/configs: move definition of CONFIG_CMD_BLOB CONFIG_CMD_BLOB must be defined in case of Secure Boot. It was earlier defined in all config files. The definition has been moved to a common file which is included by all configs. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2ed948f4 |
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31-Jul-2015 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
SECURE_BOOT: Disable IE Key feature for RAMBOOT ISBC Key Extension feature is not applicable for RAMBOOT as there is no way to retrieve the CSF Header and validated IE Key table from SRAM once CPC has been disabled. The feature is only applicable in case of NOR SECURE BOOT. Code Cleanup: The SECURE_BOOT specific defines have been moved from arch-ls102xa/config.h to arm/include/asm/fsl_secure_boot.h Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
5050f6f0 |
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15-Jun-2015 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT-Copy Boot Script on RAM For running Chain of Trust when doing Secure Boot from NAND, the Bootscript header and bootscript must be copied from NAND to RAM(DDR). The addresses and commands for the same have been defined. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
467a40df |
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15-Jun-2015 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 Secure Boot Target is added for NAND for P3041. For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In case of secure boot, this default address maps to Boot ROM. The Boot ROM code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is configured as SRAM. U-Boot binary will be located on SRAM configured at address 0xBFF00000. In the U-Boot code, TLB entries are created to map the virtual address 0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e622d9ed |
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26-Mar-2015 |
gaurav rana <gaurav.rana@freescale.com> |
powerpc/T104xD4: Add Secure boot support for T104xD4RDB platforms defconfig files are added and SFP version for these platforms is updated. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
98cb0efd |
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10-Mar-2015 |
gaurav rana <gaurav.rana@freescale.com> |
Add bootscript support to esbc_validate. 1. Default environment will be used for secure boot flow which can't be edited or saved. 2. Command for secure boot is predefined in the default environment which will run on autoboot (and autoboot is the only option allowed in case of secure boot) and it looks like this: #define CONFIG_SECBOOT \ "setenv bs_hdraddr 0xe8e00000;" \ "esbc_validate $bs_hdraddr;" \ "source $img_addr;" \ "esbc_halt;" #endif 3. Boot Script can contain esbc_validate commands and bootm command. Uboot source command used in default secure boot command will run the bootscript. 4. Command esbc_halt added to ensure either bootm executes after validation of images or core should just spin. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e04916a7 |
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26-Feb-2015 |
gaurav rana <gaurav.rana@freescale.com> |
SECURE_BOOT : enable esbc_validate command for powerpc and arm platforms. esbc_validate command uses various IP Blocks: Security Monitor, CAAM block and SFP registers. Hence the respective CONFIG's are enabled. Apart from these CONFIG_SHA_PROG_HW_ACCEL and CONFIG_RSA are also enabled. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
b3f0f632 |
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12-Dec-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: Define PBI Flash Base for C29XPCIE Secure Boot CONFIG_SYS_PBI_FLASH_BASE is defined for Secure Boot on C29X Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
f6050790 |
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24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/mpc85xx: Add T1024/T1023 SoC support Add support for Freescale T1024/T1023 SoC. The T1024 SoC includes the following function and features: - Two 64-bit Power architecture e5500 cores, up to 1.4GHz - private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC) - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration - Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI) - High-speed peripheral interfaces - Three PCI Express 2.0 controllers - Additional peripheral interfaces - One SATA 2.0 controller - Two USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/eSDHC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Two 8-channel DMA engines - Multicore programmable interrupt controller (PIC) - LCD interface (DIU) with 12 bit dual data rate - QUICC Engine block supporting TDM, HDLC, and UART - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T1024 and T1023: Feature T1024 T1023 QUICC Engine: yes no DIU: yes no Deep Sleep: yes no I2C controller: 4 3 DDR: 64-bit 32-bit IFC: 32-bit 28-bit Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e47c2a68 |
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22-Apr-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080RDB Secure Boot Target is added for T2080RDB Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080RDB. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> |
#
40678159 |
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22-Apr-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- secure boot target for t1040rdb T1040RDB.h file is removed and a unified file T104xRDB.h is created. Hence macro CONFIG_T1040 is renamed to CONFIG_T104x. Signed-off-by: Gaurav Kumar Rana <gaurav.rana@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> |
#
2d8db6d3 |
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18-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T1040QDS and T1040RDB Secure Boot Target is added for T1040QDS and T1040RDB Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T1040QDS and CONFIG_T1040RDB Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
ca4819df |
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18-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080QDS Secure Boot Target is added for T2080QDS Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080QDS. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
796a7810 |
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18-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T4240QDS and T4160QDS Secure Boot Target is added for T4240QDS and T4160QDS Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T4240QDS. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
fb4a2409 |
|
18-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS Changes: 1. L2 cache is being invalidated by Boot ROM code for e6500 core. So removing the invalidation from start.S 2. Clear the LAW and corresponding configuration for CPC. Boot ROM code uses it as hosekeeping area. 3. For Secure boot, CPC is configured as SRAM and used as house keeping area. This configuration is to be disabled once in uboot. Earlier this disabling of CPC as SRAM was happening in cpu_init_r. As a result cache invalidation function was getting skipped in case CPC is configured as SRAM.This was causing random crashes. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
f978f7c2 |
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11-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for BSC9132QDS Add NOR, SPI and SD secure boot targets for BSC9132QDS. Changes: - Debug TLB entry is not required for Secure Boot Target. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
0d2cff2d |
|
21-Aug-2013 |
Po Liu <po.liu@freescale.com> |
powerpc: add CONFIG_SECURE_BOOT condition into fsl_secure_boot.h This patch is for board config file not to add CONFIG_SECURE_BOOT condition for include the asm/fsl_secure_boot.h. Signed-off-by: Po Liu <Po.Liu@freescale.com> |
#
1a459660 |
|
08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
39bdaff4 |
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25-Mar-2013 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
SECURE BOOT - Removed deletion of TLB entries code Boot ROM code creates TLB entries for 3.5G space before entering the u-boot. Earlier we were deleting these entries after early initialization of CPU. In recent past, code has been added to invalidate all these entries before relocation of u-boot code. So this code to delete TLB entries after CPU initialization is no longer required. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Acked-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
7065b7d4 |
|
15-Dec-2010 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
powerpc/p4080: Add support for secure boot flow Pre u-boot Flow: 1. User loads the u-boot image in flash 2. PBL/Configuration word is used to create LAW for Flash at 0xc0000000 (Please note that ISBC expects all these addresses, images to be validated, entry point etc within 0 - 3.5G range) 3. ISBC validates the u-boot image, and passes control to u-boot at 0xcffffffc. Changes in u-boot: 1. Temporarily map CONFIG_SYS_MONITOR_BASE to the 1M CONFIG_SYS_PBI_FLASH_WINDOW in AS=1. (The CONFIG_SYS_PBI_FLASH_WINDOW is the address map for the flash created by PBL/configuration word within 0 - 3.5G memory range. The u-boot image at this address has been validated by ISBC code) 2. Remove TLB entries for 0 - 3.5G created by ISBC code 3. Remove the LAW entry for the CONFIG_SYS_PBI_FLASH_WINDOW created by PBL/configuration word after switch to AS = 1 Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com> Acked-by: Wood Scott-B07421 <B07421@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
ec6b37ce |
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23-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove T4160RDB board This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it. As this is the last ARCH_T4160 platform, remove that support as well. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
6c3d9933 |
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14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove T1023RBD boards and T1024RDB_SECURE_BOOT These boards have not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove them. As this is the only ARCH_T1023 platform left, remove that support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
008e9965 |
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14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove many T104x boards These boards have not been converted to CONFIG_DM_PCI, CONFIG_DM_USB or in some cases CONFIG_DM itself by the deadline. Remove them. Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a99dab1d |
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20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove Cyrus_P5020 and P5040 boards These boards have not been converted to CONFIG_DM_MMC by the deadline. Remove them. As the P5020 is the last ARCH_P5020 platform, remove that support as well. Cc: Andy Fleming <afleming@gmail.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
bf85995a |
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20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove TARGET_T1040QDS references The TARGET_T1040QDS platforms have been removed already, drop some remaining references in the code. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
bef18454 |
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07-Nov-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
freescale/powerpc: Rename the config CONFIG_SECURE_BOOT name Rename the CONFIG_SECURE_BOOT name to CONFIG_NXP_ESBC to avoid conflicts with UEFI secure boot. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ea7971f7 |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_CMD_ESBC_VALIDATE to Kconfig This converts the following to Kconfig: CONFIG_CMD_ESBC_VALIDATE Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
089df18b |
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14-May-2017 |
Tom Rini <trini@konsulko.com> |
lib: move hash CONFIG options to Kconfig Commit 94e3c8c4fd7b ("crypto/fsl - Add progressive hashing support using hardware acceleration.") created entries for CONFIG_SHA1, CONFIG_SHA256, CONFIG_SHA_HW_ACCEL, and CONFIG_SHA_PROG_HW_ACCEL. However, no defconfig has migrated to it. Complete the move by first adding additional logic to various Kconfig files to select this when required and then use the moveconfig tool. In many cases we can select these because they are required to implement other drivers. We also correct how we include the various hashing algorithms in SPL. This commit was generated as follows (after Kconfig additions): [1] tools/moveconfig.py -y SHA1 SHA256 SHA_HW_ACCEL [2] tools/moveconfig.py -y SHA_PROG_HW_ACCEL Note: We cannot move SHA_HW_ACCEL and SHA_PROG_HW_ACCEL simultaneously because there is dependency between them. Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com> Cc: Naveen Burmi <NaveenBurmi@freescale.com> Cc: Po Liu <po.liu@freescale.com> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Priyanka Jain <Priyanka.Jain@freescale.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Chander Kashyap <k.chander@samsung.com> Cc: Steve Rae <steve.rae@raedomain.com> Cc: Dirk Eibach <eibach@gdsys.de> Cc: Feng Li <feng.li_2@nxp.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Sumit Garg <sumit.garg@nxp.com> Cc: Mingkai Hu <Mingkai.Hu@freescale.com> Cc: York Sun <york.sun@nxp.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Akshay Saraswat <akshay.s@samsung.com> Cc: Heiko Schocher <hs@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
c04b9b34 |
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26-Apr-2017 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_CMD_BLOB to Kconfig This converts the following to Kconfig: CONFIG_CMD_BLOB Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Add imply CMD_BLOB under CHAIN_OF_TRUST] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
0645c23a |
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30-Mar-2017 |
VINITHA PILLAI <vinitha.pillai@nxp.com> |
powerpc: T1042RDB: SECURE BOOT: Remove CONFIG_CMD_BLOB from SPL compilation BLOB feature is not required during SPL compilation. Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
28522678 |
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01-Mar-2017 |
Tom Rini <trini@konsulko.com> |
Freescale/NXP: Migrate CONFIG_FSL_CAAM to defconfigs In some cases this is absolutely required, so select this for some secure features. This also requires migration of RSA_FREESCALE_EXP Cc: Ruchika Gupta <ruchika.gupta@nxp.com> Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com> Cc: Naveen Burmi <NaveenBurmi@freescale.com> Cc: Po Liu <po.liu@freescale.com> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Priyanka Jain <Priyanka.Jain@freescale.com> Cc: Sumit Garg <sumit.garg@nxp.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Feng Li <feng.li_2@nxp.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Mingkai Hu <Mingkai.Hu@freescale.com> Cc: York Sun <york.sun@nxp.com> Cc: Saksham Jain <saksham.jain@nxp.freescale.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
88077715 |
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22-Jan-2017 |
Tom Rini <trini@konsulko.com> |
NXP: Introduce board/freescale/common/Kconfig and migrate CHAIN_OF_TRUST Introduce board/freescale/common/Kconfig so that we have a single place for CONFIG options that are shared between ARM and PowerPC NXP platforms. Cc: York Sun <york.sun@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3788b451 |
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21-Jan-2017 |
Jagan Teki <jagan@openedev.com> |
config: Move CONFIG_BOARD_LATE_INIT to defconfigs Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jagan@openedev.com> |
#
a1055038 |
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28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T104xQDS: Remove macro CONFIG_T104xD4QDS Remove this macro. It was added by e622d9ed but actually wasn't used. Signed-off-by: York Sun <york.sun@nxp.com> |
#
86e0a313 |
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28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T2080RDB: Remove macro CONFIG_T2080RDB Use TARGET_T2080RDB from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
80d26188 |
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28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T2080QDS: Remove macro T2080QDS Use TARGET_T2080QDS from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
f4f66940 |
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28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1040QDS: Remove macro CONFIG_T1040QDS Use TARGET_T1040QDS from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
673c01c7 |
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21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4240QDS: Remove macro CONFIG_T4240QDS Use CONFIG_TARGET_T4240QDS instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9c21d06c |
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21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4160QDS: Separate from T4240QDS in Kconfig Use TARGET_T4160QDS to simplify Kconfig options. Signed-off-by: York Sun <york.sun@nxp.com> |
#
78e56995 |
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21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T104xRDB: Remove macro CONFIG_T104xRDB and T104xD4RDB CONFIG_T104xRDB is defined in T104xRDB.h, so it is always enabled for all T1040RDB, T1040D4RDB, T1042RDB, T1042D4RDB, T1042RDB_PI. CONFIG_T104XD4RDB is defined for all T1040D4RDB, T1042D4RDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e5d5f5a8 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1024: Remove macro CONFIG_PPC_T1024 Replace CONFIG_PPC_T1024 with ARCH_T1024 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5ff3f41d |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1023: Remove macro CONFIG_PPC_T1023 Replace CONFIG_PPC_T1023 with ARCH_T1023 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
d46a4a13 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: B4860QDS: Remove macro CONFIG_B4860QDS Use CONFIG_TARGET_B4860QDS instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
95390360 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P5040: Remove macro CONFIG_P5040 Replace CONFIG_P5040 with ARCH_P5040 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
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cefe11cd |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P5020: Remove macro CONFIG_PPC_P5020 Replace CONFIG_PPC_P5020 with ARCH_P5020 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e71372cb |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P4080: Remove macro CONFIG_PPC_P4080 Replace CONFIG_PPC_P4080 with ARCH_P4080 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
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5e5fdd2d |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P3041: Remove macro CONFIG_PPC_P3041 Replace CONFIG_PPC_P3041 with ARCH_P3041 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ce040c83 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P2041: Remove macro CONFIG_PPC_P2041 Replace CONFIG_PPC_P2041 with ARCH_P2041 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
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ebccf255 |
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16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: C29XPCIE: Remove macro CONFIG_C29XPCIE Use CONFIG_TARGET_C29XPCIE instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a202b9f8 |
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15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: BSC9132QDS: Remove CONFIG_BSC9132QDS macro Use CONFIG_TARGET_BSC9132QDS from Kconfig option, remove CONFIG_BSC9132QDS macro. Signed-off-by: York Sun <york.sun@nxp.com> |
#
d3662dff |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_SPL_DRIVERS_MISC_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org> |
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d3e7e2b2 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_SPL_HASH_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
dbdaeee4 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_SPL_CRYPTO_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d3c1f467 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Move existing use of CONFIG_SPL_RSA to Kconfig A few boards define this in a header file which is incorrect. It means that Kconfig options that rely on this cannot be used. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3433a693 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Move existing use of CONFIG_SPL_DM to Kconfig A few boards define this in a header file which is incorrect. It means that Kconfig options that rely on this cannot be used. Move it. Note that quite a few boards defined this options but do not appear to actually use SPL: BSC9132QDS_NOR_DDRCLK100_SECURE BSC9132QDS_NOR_DDRCLK133_SECURE BSC9132QDS_SDCARD_DDRCLK100_SECURE BSC9132QDS_SDCARD_DDRCLK133_SECURE BSC9132QDS_SPIFLASH_DDRCLK100_SECURE BSC9132QDS_SPIFLASH_DDRCLK133_SECURE C29XPCIE_NOR_SECBOOT P1010RDB-PA_36BIT_NAND_SECBOOT P1010RDB-PA_36BIT_SPIFLASH_SECBOOT P1010RDB-PA_NAND_SECBOOT P1010RDB-PA_NOR_SECBOOT P1010RDB-PB_36BIT_NOR_SECBOOT P1010RDB-PB_36BIT_SPIFLASH_SECBOOT P1010RDB-PB_NAND_SECBOOT P1010RDB-PB_NOR_SECBOOT P3041DS_SECURE_BOOT P4080DS_SECURE_BOOT P5020DS_NAND_SECURE_BOOT P5040DS_SECURE_BOOT T1023RDB_SECURE_BOOT T1024QDS_DDR4_SECURE_BOOT T1024QDS_SECURE_BOOT T1024RDB_SECURE_BOOT T1040RDB_SECURE_BOOT T1042D4RDB_SECURE_BOOT T1042RDB_SECURE_BOOT T2080QDS_SECURE_BOOT T2080RDB_SECURE_BOOT T4160QDS_SECURE_BOOT T4240QDS_SECURE_BOOT ls1021aqds_nor_SECURE_BOOT ls1021atwr_nor_SECURE_BOOT ls1043ardb_SECURE_BOOT For these boards CONFIG_SPL_DM will no-longer be defined in SPL. But since they apparently don't have an SPL, this should not matter. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
b63f8a43 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
arm: fsl: Adjust ordering of #ifndef CONFIG_SPL_BUILD The secure boot header files incorrectly define SPL options only if CONFIG_SPL_BUILD is defined. This means that the options are only enabled in an SPL build, and not with a normal 'make xxx_defconfig'. This means that moveconfig.py cannot work, since it sees the options as disabled even when they may be manually enabled in an SPL build. Fix this by changing the order. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
69d4b48c |
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14-Jun-2016 |
Sumit Garg <sumit.garg@nxp.com> |
SECURE_BOOT: Enable SD as a source for bootscript Add support for reading bootscript and bootscript header from SD. Also renamed macros *_FLASH to *_DEVICE to represent SD alongwith NAND and NOR flash. Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
aa36c84e |
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13-Jul-2016 |
Sumit Garg <sumit.garg@nxp.com> |
powerpc/mpc85xx: T104x: Add nand secure boot target For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In non-secure boot scenario from NAND, this address will map to CPC configured as SRAM. But in case of secure boot, this default address always maps to IBR (Internal Boot ROM). The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. For secure boot target from NAND, the text base for SPL is kept same as non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000) As a the virtual and physical address of CPC would be different. The virtual address 0xFFFx_xxxx needs to be mapped to physical address 0xBFFx_xxxx. Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000 and update DCFG SCRTACH1 register with location of Header required for secure boot. The changes are similar to commit 467a40dfe35f48d830f01a72617207d03ca85b4d powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC is only 256K and thus SPL framework is used. The changes are only applicable for SPL U-Boot running out of CPC SRAM and not the next level U-Boot loaded on DDR. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
8f01397b |
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13-Jul-2016 |
Sumit Garg <sumit.garg@nxp.com> |
powerpc/mpc85xx: SECURE BOOT- Enable chain of trust in SPL As part of Chain of Trust for Secure boot, the SPL U-Boot will validate the next level U-boot image. Add a new function spl_validate_uboot to perform the validation. Enable hardware crypto operations in SPL using SEC block. In case of Secure Boot, PAMU is not bypassed. For allowing SEC block access to CPC configured as SRAM, configure PAMU. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
73223f0e |
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22-Feb-2016 |
Simon Glass <sjg@chromium.org> |
Kconfig: Move CONFIG_FIT and related options to Kconfig There are already two FIT options in Kconfig but the CONFIG options are still in the header files. We need to do a proper move to fix this. Move these options to Kconfig and tidy up board configuration: CONFIG_FIT CONFIG_OF_BOARD_SETUP CONFIG_OF_SYSTEM_SETUP CONFIG_FIT_SIGNATURE CONFIG_FIT_BEST_MATCH CONFIG_FIT_VERBOSE CONFIG_OF_STDOUT_VIA_ALIAS CONFIG_RSA Unfortunately the first one is a little complicated. We need to make sure this option is not enabled in SPL by this change. Also this option is enabled automatically in the host builds by defining CONFIG_FIT in the image.h file. To solve this, add a new IMAGE_USE_FIT #define which can be used in files that are built on the host but must also build for U-Boot and SPL. Note: Masahiro's moveconfig.py script is amazing. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Add microblaze change, various configs/ re-applies] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
9e971632 |
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22-Feb-2016 |
Simon Glass <sjg@chromium.org> |
freescale: Remove CONFIG_DM from header files Kconfig options must defined in the defconfig files. Since RSA_SOFTWARE_EXP relies on CONFIG_DM, unless it is set in kconfig we cannot enable RSA. Remove the hacks which enable CONFIG_DM in header files and update the defconfig. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d0a6d7ce |
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22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: enable chain of trust for PowerPC platforms Chain of Trust is enabled for PowerPC platforms for Secure Boot. CONFIG_BOARD_LATE_INIT is defined. In board_late_init(), fsl_setenv_chain_of_trust() is called which will perform the following: - If boot mode is non-secure, return (No Change) - If boot mode is secure, set the following environmet variables: bootdelay = 0 (To disable Boot Prompt) bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
bdc22074 |
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22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: split the secure boot functionality in two parts There are two phases in Secure Boot 1. ISBC: In BootROM, validate the BootLoader (U-Boot). 2. ESBC: In U-Boot, continuing the Chain of Trust by validating and booting LINUX. For ESBC phase, there is no difference in SoC's based on ARM or PowerPC cores. But the exit conditions after ISBC phase i.e. entry conditions for U-Boot are different for ARM and PowerPC. PowerPC: If Secure Boot is executed, a separate U-Boot target is required which must be compiled with a diffrent Text Base as compared to Non-Secure Boot. There are some LAW and TLB settings which are required specifically for Secure Boot scenario. ARM: ARM based SoC's have a fixed memory map and exit conditions from BootROM are same irrespective of boot mode (Secure or Non-Secure). Thus the current Secure Boot functionlity has been split into two parts: CONFIG_CHAIN_OF_TRUST This will have the following functionality as part of U-Boot: 1. Enable commands like esbc_validate, esbc_halt 2. Change the environment settings based on bootmode, determined at run time: - If bootmode is non-secure, no change - If bootmode is secure, set the following: - bootdelay = 0 (Don't give boot prompt) - bootcmd = Validate and execute the bootscript. CONFIG_SECURE_BOOT This is defined only for creating a different compile time target for secure boot. Traditionally, both these functionalities were defined under CONFIG_SECURE_BOOT. This patch is aimed at removing the requirement for a separate Secure Boot target for ARM based SoC's. CONFIG_CHAIN_OF_TRUST will be defined and boot mode will be determine at run time. Another Security Requirement for running CHAIN_OF_TRUST is that U-Boot environemnt must not be picked from flash/external memory. This cannot be done based on bootmode at run time in current U-Boot architecture. Once this dependency is resolved, no separate SECURE_BOOT target will be required for ARM based SoC's. Currently, the only code under CONFIG_SECURE_BOOT for ARM SoC's is defining CONFIG_ENV_IS_NOWHERE Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
74eecd82 |
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22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: include/configs: move definition of CONFIG_CMD_BLOB CONFIG_CMD_BLOB must be defined in case of Secure Boot. It was earlier defined in all config files. The definition has been moved to a common file which is included by all configs. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2ed948f4 |
|
31-Jul-2015 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
SECURE_BOOT: Disable IE Key feature for RAMBOOT ISBC Key Extension feature is not applicable for RAMBOOT as there is no way to retrieve the CSF Header and validated IE Key table from SRAM once CPC has been disabled. The feature is only applicable in case of NOR SECURE BOOT. Code Cleanup: The SECURE_BOOT specific defines have been moved from arch-ls102xa/config.h to arm/include/asm/fsl_secure_boot.h Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
5050f6f0 |
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15-Jun-2015 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT-Copy Boot Script on RAM For running Chain of Trust when doing Secure Boot from NAND, the Bootscript header and bootscript must be copied from NAND to RAM(DDR). The addresses and commands for the same have been defined. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
467a40df |
|
15-Jun-2015 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 Secure Boot Target is added for NAND for P3041. For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In case of secure boot, this default address maps to Boot ROM. The Boot ROM code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is configured as SRAM. U-Boot binary will be located on SRAM configured at address 0xBFF00000. In the U-Boot code, TLB entries are created to map the virtual address 0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e622d9ed |
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26-Mar-2015 |
gaurav rana <gaurav.rana@freescale.com> |
powerpc/T104xD4: Add Secure boot support for T104xD4RDB platforms defconfig files are added and SFP version for these platforms is updated. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
98cb0efd |
|
10-Mar-2015 |
gaurav rana <gaurav.rana@freescale.com> |
Add bootscript support to esbc_validate. 1. Default environment will be used for secure boot flow which can't be edited or saved. 2. Command for secure boot is predefined in the default environment which will run on autoboot (and autoboot is the only option allowed in case of secure boot) and it looks like this: #define CONFIG_SECBOOT \ "setenv bs_hdraddr 0xe8e00000;" \ "esbc_validate $bs_hdraddr;" \ "source $img_addr;" \ "esbc_halt;" #endif 3. Boot Script can contain esbc_validate commands and bootm command. Uboot source command used in default secure boot command will run the bootscript. 4. Command esbc_halt added to ensure either bootm executes after validation of images or core should just spin. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e04916a7 |
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26-Feb-2015 |
gaurav rana <gaurav.rana@freescale.com> |
SECURE_BOOT : enable esbc_validate command for powerpc and arm platforms. esbc_validate command uses various IP Blocks: Security Monitor, CAAM block and SFP registers. Hence the respective CONFIG's are enabled. Apart from these CONFIG_SHA_PROG_HW_ACCEL and CONFIG_RSA are also enabled. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
b3f0f632 |
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12-Dec-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: Define PBI Flash Base for C29XPCIE Secure Boot CONFIG_SYS_PBI_FLASH_BASE is defined for Secure Boot on C29X Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
f6050790 |
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24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/mpc85xx: Add T1024/T1023 SoC support Add support for Freescale T1024/T1023 SoC. The T1024 SoC includes the following function and features: - Two 64-bit Power architecture e5500 cores, up to 1.4GHz - private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC) - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration - Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI) - High-speed peripheral interfaces - Three PCI Express 2.0 controllers - Additional peripheral interfaces - One SATA 2.0 controller - Two USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/eSDHC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Two 8-channel DMA engines - Multicore programmable interrupt controller (PIC) - LCD interface (DIU) with 12 bit dual data rate - QUICC Engine block supporting TDM, HDLC, and UART - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T1024 and T1023: Feature T1024 T1023 QUICC Engine: yes no DIU: yes no Deep Sleep: yes no I2C controller: 4 3 DDR: 64-bit 32-bit IFC: 32-bit 28-bit Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e47c2a68 |
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22-Apr-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080RDB Secure Boot Target is added for T2080RDB Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080RDB. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> |
#
40678159 |
|
22-Apr-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- secure boot target for t1040rdb T1040RDB.h file is removed and a unified file T104xRDB.h is created. Hence macro CONFIG_T1040 is renamed to CONFIG_T104x. Signed-off-by: Gaurav Kumar Rana <gaurav.rana@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> |
#
2d8db6d3 |
|
18-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T1040QDS and T1040RDB Secure Boot Target is added for T1040QDS and T1040RDB Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T1040QDS and CONFIG_T1040RDB Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
ca4819df |
|
18-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080QDS Secure Boot Target is added for T2080QDS Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080QDS. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
796a7810 |
|
18-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T4240QDS and T4160QDS Secure Boot Target is added for T4240QDS and T4160QDS Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T4240QDS. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
fb4a2409 |
|
18-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS Changes: 1. L2 cache is being invalidated by Boot ROM code for e6500 core. So removing the invalidation from start.S 2. Clear the LAW and corresponding configuration for CPC. Boot ROM code uses it as hosekeeping area. 3. For Secure boot, CPC is configured as SRAM and used as house keeping area. This configuration is to be disabled once in uboot. Earlier this disabling of CPC as SRAM was happening in cpu_init_r. As a result cache invalidation function was getting skipped in case CPC is configured as SRAM.This was causing random crashes. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
f978f7c2 |
|
11-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for BSC9132QDS Add NOR, SPI and SD secure boot targets for BSC9132QDS. Changes: - Debug TLB entry is not required for Secure Boot Target. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
0d2cff2d |
|
21-Aug-2013 |
Po Liu <po.liu@freescale.com> |
powerpc: add CONFIG_SECURE_BOOT condition into fsl_secure_boot.h This patch is for board config file not to add CONFIG_SECURE_BOOT condition for include the asm/fsl_secure_boot.h. Signed-off-by: Po Liu <Po.Liu@freescale.com> |
#
1a459660 |
|
08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
39bdaff4 |
|
25-Mar-2013 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
SECURE BOOT - Removed deletion of TLB entries code Boot ROM code creates TLB entries for 3.5G space before entering the u-boot. Earlier we were deleting these entries after early initialization of CPU. In recent past, code has been added to invalidate all these entries before relocation of u-boot code. So this code to delete TLB entries after CPU initialization is no longer required. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Acked-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
7065b7d4 |
|
15-Dec-2010 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
powerpc/p4080: Add support for secure boot flow Pre u-boot Flow: 1. User loads the u-boot image in flash 2. PBL/Configuration word is used to create LAW for Flash at 0xc0000000 (Please note that ISBC expects all these addresses, images to be validated, entry point etc within 0 - 3.5G range) 3. ISBC validates the u-boot image, and passes control to u-boot at 0xcffffffc. Changes in u-boot: 1. Temporarily map CONFIG_SYS_MONITOR_BASE to the 1M CONFIG_SYS_PBI_FLASH_WINDOW in AS=1. (The CONFIG_SYS_PBI_FLASH_WINDOW is the address map for the flash created by PBL/configuration word within 0 - 3.5G memory range. The u-boot image at this address has been validated by ISBC code) 2. Remove TLB entries for 0 - 3.5G created by ISBC code 3. Remove the LAW entry for the CONFIG_SYS_PBI_FLASH_WINDOW created by PBL/configuration word after switch to AS = 1 Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com> Acked-by: Wood Scott-B07421 <B07421@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
a99dab1d |
|
20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove Cyrus_P5020 and P5040 boards These boards have not been converted to CONFIG_DM_MMC by the deadline. Remove them. As the P5020 is the last ARCH_P5020 platform, remove that support as well. Cc: Andy Fleming <afleming@gmail.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
bf85995a |
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20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove TARGET_T1040QDS references The TARGET_T1040QDS platforms have been removed already, drop some remaining references in the code. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
bef18454 |
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07-Nov-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
freescale/powerpc: Rename the config CONFIG_SECURE_BOOT name Rename the CONFIG_SECURE_BOOT name to CONFIG_NXP_ESBC to avoid conflicts with UEFI secure boot. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ea7971f7 |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_CMD_ESBC_VALIDATE to Kconfig This converts the following to Kconfig: CONFIG_CMD_ESBC_VALIDATE Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
089df18b |
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14-May-2017 |
Tom Rini <trini@konsulko.com> |
lib: move hash CONFIG options to Kconfig Commit 94e3c8c4fd7b ("crypto/fsl - Add progressive hashing support using hardware acceleration.") created entries for CONFIG_SHA1, CONFIG_SHA256, CONFIG_SHA_HW_ACCEL, and CONFIG_SHA_PROG_HW_ACCEL. However, no defconfig has migrated to it. Complete the move by first adding additional logic to various Kconfig files to select this when required and then use the moveconfig tool. In many cases we can select these because they are required to implement other drivers. We also correct how we include the various hashing algorithms in SPL. This commit was generated as follows (after Kconfig additions): [1] tools/moveconfig.py -y SHA1 SHA256 SHA_HW_ACCEL [2] tools/moveconfig.py -y SHA_PROG_HW_ACCEL Note: We cannot move SHA_HW_ACCEL and SHA_PROG_HW_ACCEL simultaneously because there is dependency between them. Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com> Cc: Naveen Burmi <NaveenBurmi@freescale.com> Cc: Po Liu <po.liu@freescale.com> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Priyanka Jain <Priyanka.Jain@freescale.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Chander Kashyap <k.chander@samsung.com> Cc: Steve Rae <steve.rae@raedomain.com> Cc: Dirk Eibach <eibach@gdsys.de> Cc: Feng Li <feng.li_2@nxp.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Sumit Garg <sumit.garg@nxp.com> Cc: Mingkai Hu <Mingkai.Hu@freescale.com> Cc: York Sun <york.sun@nxp.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Akshay Saraswat <akshay.s@samsung.com> Cc: Heiko Schocher <hs@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
c04b9b34 |
|
26-Apr-2017 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_CMD_BLOB to Kconfig This converts the following to Kconfig: CONFIG_CMD_BLOB Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Add imply CMD_BLOB under CHAIN_OF_TRUST] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
0645c23a |
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30-Mar-2017 |
VINITHA PILLAI <vinitha.pillai@nxp.com> |
powerpc: T1042RDB: SECURE BOOT: Remove CONFIG_CMD_BLOB from SPL compilation BLOB feature is not required during SPL compilation. Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
28522678 |
|
01-Mar-2017 |
Tom Rini <trini@konsulko.com> |
Freescale/NXP: Migrate CONFIG_FSL_CAAM to defconfigs In some cases this is absolutely required, so select this for some secure features. This also requires migration of RSA_FREESCALE_EXP Cc: Ruchika Gupta <ruchika.gupta@nxp.com> Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com> Cc: Naveen Burmi <NaveenBurmi@freescale.com> Cc: Po Liu <po.liu@freescale.com> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Priyanka Jain <Priyanka.Jain@freescale.com> Cc: Sumit Garg <sumit.garg@nxp.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Feng Li <feng.li_2@nxp.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Mingkai Hu <Mingkai.Hu@freescale.com> Cc: York Sun <york.sun@nxp.com> Cc: Saksham Jain <saksham.jain@nxp.freescale.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
88077715 |
|
22-Jan-2017 |
Tom Rini <trini@konsulko.com> |
NXP: Introduce board/freescale/common/Kconfig and migrate CHAIN_OF_TRUST Introduce board/freescale/common/Kconfig so that we have a single place for CONFIG options that are shared between ARM and PowerPC NXP platforms. Cc: York Sun <york.sun@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3788b451 |
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21-Jan-2017 |
Jagan Teki <jagan@openedev.com> |
config: Move CONFIG_BOARD_LATE_INIT to defconfigs Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jagan@openedev.com> |
#
a1055038 |
|
28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T104xQDS: Remove macro CONFIG_T104xD4QDS Remove this macro. It was added by e622d9ed but actually wasn't used. Signed-off-by: York Sun <york.sun@nxp.com> |
#
86e0a313 |
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28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T2080RDB: Remove macro CONFIG_T2080RDB Use TARGET_T2080RDB from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
80d26188 |
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28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T2080QDS: Remove macro T2080QDS Use TARGET_T2080QDS from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
f4f66940 |
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28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1040QDS: Remove macro CONFIG_T1040QDS Use TARGET_T1040QDS from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
673c01c7 |
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21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4240QDS: Remove macro CONFIG_T4240QDS Use CONFIG_TARGET_T4240QDS instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9c21d06c |
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21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4160QDS: Separate from T4240QDS in Kconfig Use TARGET_T4160QDS to simplify Kconfig options. Signed-off-by: York Sun <york.sun@nxp.com> |
#
78e56995 |
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21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T104xRDB: Remove macro CONFIG_T104xRDB and T104xD4RDB CONFIG_T104xRDB is defined in T104xRDB.h, so it is always enabled for all T1040RDB, T1040D4RDB, T1042RDB, T1042D4RDB, T1042RDB_PI. CONFIG_T104XD4RDB is defined for all T1040D4RDB, T1042D4RDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e5d5f5a8 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1024: Remove macro CONFIG_PPC_T1024 Replace CONFIG_PPC_T1024 with ARCH_T1024 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5ff3f41d |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1023: Remove macro CONFIG_PPC_T1023 Replace CONFIG_PPC_T1023 with ARCH_T1023 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
d46a4a13 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: B4860QDS: Remove macro CONFIG_B4860QDS Use CONFIG_TARGET_B4860QDS instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
95390360 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P5040: Remove macro CONFIG_P5040 Replace CONFIG_P5040 with ARCH_P5040 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
cefe11cd |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P5020: Remove macro CONFIG_PPC_P5020 Replace CONFIG_PPC_P5020 with ARCH_P5020 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e71372cb |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P4080: Remove macro CONFIG_PPC_P4080 Replace CONFIG_PPC_P4080 with ARCH_P4080 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5e5fdd2d |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P3041: Remove macro CONFIG_PPC_P3041 Replace CONFIG_PPC_P3041 with ARCH_P3041 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ce040c83 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P2041: Remove macro CONFIG_PPC_P2041 Replace CONFIG_PPC_P2041 with ARCH_P2041 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ebccf255 |
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16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: C29XPCIE: Remove macro CONFIG_C29XPCIE Use CONFIG_TARGET_C29XPCIE instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a202b9f8 |
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15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: BSC9132QDS: Remove CONFIG_BSC9132QDS macro Use CONFIG_TARGET_BSC9132QDS from Kconfig option, remove CONFIG_BSC9132QDS macro. Signed-off-by: York Sun <york.sun@nxp.com> |
#
d3662dff |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_SPL_DRIVERS_MISC_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d3e7e2b2 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_SPL_HASH_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
dbdaeee4 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_SPL_CRYPTO_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d3c1f467 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Move existing use of CONFIG_SPL_RSA to Kconfig A few boards define this in a header file which is incorrect. It means that Kconfig options that rely on this cannot be used. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3433a693 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Move existing use of CONFIG_SPL_DM to Kconfig A few boards define this in a header file which is incorrect. It means that Kconfig options that rely on this cannot be used. Move it. Note that quite a few boards defined this options but do not appear to actually use SPL: BSC9132QDS_NOR_DDRCLK100_SECURE BSC9132QDS_NOR_DDRCLK133_SECURE BSC9132QDS_SDCARD_DDRCLK100_SECURE BSC9132QDS_SDCARD_DDRCLK133_SECURE BSC9132QDS_SPIFLASH_DDRCLK100_SECURE BSC9132QDS_SPIFLASH_DDRCLK133_SECURE C29XPCIE_NOR_SECBOOT P1010RDB-PA_36BIT_NAND_SECBOOT P1010RDB-PA_36BIT_SPIFLASH_SECBOOT P1010RDB-PA_NAND_SECBOOT P1010RDB-PA_NOR_SECBOOT P1010RDB-PB_36BIT_NOR_SECBOOT P1010RDB-PB_36BIT_SPIFLASH_SECBOOT P1010RDB-PB_NAND_SECBOOT P1010RDB-PB_NOR_SECBOOT P3041DS_SECURE_BOOT P4080DS_SECURE_BOOT P5020DS_NAND_SECURE_BOOT P5040DS_SECURE_BOOT T1023RDB_SECURE_BOOT T1024QDS_DDR4_SECURE_BOOT T1024QDS_SECURE_BOOT T1024RDB_SECURE_BOOT T1040RDB_SECURE_BOOT T1042D4RDB_SECURE_BOOT T1042RDB_SECURE_BOOT T2080QDS_SECURE_BOOT T2080RDB_SECURE_BOOT T4160QDS_SECURE_BOOT T4240QDS_SECURE_BOOT ls1021aqds_nor_SECURE_BOOT ls1021atwr_nor_SECURE_BOOT ls1043ardb_SECURE_BOOT For these boards CONFIG_SPL_DM will no-longer be defined in SPL. But since they apparently don't have an SPL, this should not matter. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
b63f8a43 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
arm: fsl: Adjust ordering of #ifndef CONFIG_SPL_BUILD The secure boot header files incorrectly define SPL options only if CONFIG_SPL_BUILD is defined. This means that the options are only enabled in an SPL build, and not with a normal 'make xxx_defconfig'. This means that moveconfig.py cannot work, since it sees the options as disabled even when they may be manually enabled in an SPL build. Fix this by changing the order. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
69d4b48c |
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14-Jun-2016 |
Sumit Garg <sumit.garg@nxp.com> |
SECURE_BOOT: Enable SD as a source for bootscript Add support for reading bootscript and bootscript header from SD. Also renamed macros *_FLASH to *_DEVICE to represent SD alongwith NAND and NOR flash. Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
aa36c84e |
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13-Jul-2016 |
Sumit Garg <sumit.garg@nxp.com> |
powerpc/mpc85xx: T104x: Add nand secure boot target For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In non-secure boot scenario from NAND, this address will map to CPC configured as SRAM. But in case of secure boot, this default address always maps to IBR (Internal Boot ROM). The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. For secure boot target from NAND, the text base for SPL is kept same as non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000) As a the virtual and physical address of CPC would be different. The virtual address 0xFFFx_xxxx needs to be mapped to physical address 0xBFFx_xxxx. Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000 and update DCFG SCRTACH1 register with location of Header required for secure boot. The changes are similar to commit 467a40dfe35f48d830f01a72617207d03ca85b4d powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC is only 256K and thus SPL framework is used. The changes are only applicable for SPL U-Boot running out of CPC SRAM and not the next level U-Boot loaded on DDR. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
8f01397b |
|
13-Jul-2016 |
Sumit Garg <sumit.garg@nxp.com> |
powerpc/mpc85xx: SECURE BOOT- Enable chain of trust in SPL As part of Chain of Trust for Secure boot, the SPL U-Boot will validate the next level U-boot image. Add a new function spl_validate_uboot to perform the validation. Enable hardware crypto operations in SPL using SEC block. In case of Secure Boot, PAMU is not bypassed. For allowing SEC block access to CPC configured as SRAM, configure PAMU. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
73223f0e |
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22-Feb-2016 |
Simon Glass <sjg@chromium.org> |
Kconfig: Move CONFIG_FIT and related options to Kconfig There are already two FIT options in Kconfig but the CONFIG options are still in the header files. We need to do a proper move to fix this. Move these options to Kconfig and tidy up board configuration: CONFIG_FIT CONFIG_OF_BOARD_SETUP CONFIG_OF_SYSTEM_SETUP CONFIG_FIT_SIGNATURE CONFIG_FIT_BEST_MATCH CONFIG_FIT_VERBOSE CONFIG_OF_STDOUT_VIA_ALIAS CONFIG_RSA Unfortunately the first one is a little complicated. We need to make sure this option is not enabled in SPL by this change. Also this option is enabled automatically in the host builds by defining CONFIG_FIT in the image.h file. To solve this, add a new IMAGE_USE_FIT #define which can be used in files that are built on the host but must also build for U-Boot and SPL. Note: Masahiro's moveconfig.py script is amazing. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Add microblaze change, various configs/ re-applies] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
9e971632 |
|
22-Feb-2016 |
Simon Glass <sjg@chromium.org> |
freescale: Remove CONFIG_DM from header files Kconfig options must defined in the defconfig files. Since RSA_SOFTWARE_EXP relies on CONFIG_DM, unless it is set in kconfig we cannot enable RSA. Remove the hacks which enable CONFIG_DM in header files and update the defconfig. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d0a6d7ce |
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22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: enable chain of trust for PowerPC platforms Chain of Trust is enabled for PowerPC platforms for Secure Boot. CONFIG_BOARD_LATE_INIT is defined. In board_late_init(), fsl_setenv_chain_of_trust() is called which will perform the following: - If boot mode is non-secure, return (No Change) - If boot mode is secure, set the following environmet variables: bootdelay = 0 (To disable Boot Prompt) bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
bdc22074 |
|
22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: split the secure boot functionality in two parts There are two phases in Secure Boot 1. ISBC: In BootROM, validate the BootLoader (U-Boot). 2. ESBC: In U-Boot, continuing the Chain of Trust by validating and booting LINUX. For ESBC phase, there is no difference in SoC's based on ARM or PowerPC cores. But the exit conditions after ISBC phase i.e. entry conditions for U-Boot are different for ARM and PowerPC. PowerPC: If Secure Boot is executed, a separate U-Boot target is required which must be compiled with a diffrent Text Base as compared to Non-Secure Boot. There are some LAW and TLB settings which are required specifically for Secure Boot scenario. ARM: ARM based SoC's have a fixed memory map and exit conditions from BootROM are same irrespective of boot mode (Secure or Non-Secure). Thus the current Secure Boot functionlity has been split into two parts: CONFIG_CHAIN_OF_TRUST This will have the following functionality as part of U-Boot: 1. Enable commands like esbc_validate, esbc_halt 2. Change the environment settings based on bootmode, determined at run time: - If bootmode is non-secure, no change - If bootmode is secure, set the following: - bootdelay = 0 (Don't give boot prompt) - bootcmd = Validate and execute the bootscript. CONFIG_SECURE_BOOT This is defined only for creating a different compile time target for secure boot. Traditionally, both these functionalities were defined under CONFIG_SECURE_BOOT. This patch is aimed at removing the requirement for a separate Secure Boot target for ARM based SoC's. CONFIG_CHAIN_OF_TRUST will be defined and boot mode will be determine at run time. Another Security Requirement for running CHAIN_OF_TRUST is that U-Boot environemnt must not be picked from flash/external memory. This cannot be done based on bootmode at run time in current U-Boot architecture. Once this dependency is resolved, no separate SECURE_BOOT target will be required for ARM based SoC's. Currently, the only code under CONFIG_SECURE_BOOT for ARM SoC's is defining CONFIG_ENV_IS_NOWHERE Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
74eecd82 |
|
22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: include/configs: move definition of CONFIG_CMD_BLOB CONFIG_CMD_BLOB must be defined in case of Secure Boot. It was earlier defined in all config files. The definition has been moved to a common file which is included by all configs. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2ed948f4 |
|
31-Jul-2015 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
SECURE_BOOT: Disable IE Key feature for RAMBOOT ISBC Key Extension feature is not applicable for RAMBOOT as there is no way to retrieve the CSF Header and validated IE Key table from SRAM once CPC has been disabled. The feature is only applicable in case of NOR SECURE BOOT. Code Cleanup: The SECURE_BOOT specific defines have been moved from arch-ls102xa/config.h to arm/include/asm/fsl_secure_boot.h Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
5050f6f0 |
|
15-Jun-2015 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT-Copy Boot Script on RAM For running Chain of Trust when doing Secure Boot from NAND, the Bootscript header and bootscript must be copied from NAND to RAM(DDR). The addresses and commands for the same have been defined. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
467a40df |
|
15-Jun-2015 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 Secure Boot Target is added for NAND for P3041. For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In case of secure boot, this default address maps to Boot ROM. The Boot ROM code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is configured as SRAM. U-Boot binary will be located on SRAM configured at address 0xBFF00000. In the U-Boot code, TLB entries are created to map the virtual address 0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e622d9ed |
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26-Mar-2015 |
gaurav rana <gaurav.rana@freescale.com> |
powerpc/T104xD4: Add Secure boot support for T104xD4RDB platforms defconfig files are added and SFP version for these platforms is updated. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
98cb0efd |
|
10-Mar-2015 |
gaurav rana <gaurav.rana@freescale.com> |
Add bootscript support to esbc_validate. 1. Default environment will be used for secure boot flow which can't be edited or saved. 2. Command for secure boot is predefined in the default environment which will run on autoboot (and autoboot is the only option allowed in case of secure boot) and it looks like this: #define CONFIG_SECBOOT \ "setenv bs_hdraddr 0xe8e00000;" \ "esbc_validate $bs_hdraddr;" \ "source $img_addr;" \ "esbc_halt;" #endif 3. Boot Script can contain esbc_validate commands and bootm command. Uboot source command used in default secure boot command will run the bootscript. 4. Command esbc_halt added to ensure either bootm executes after validation of images or core should just spin. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e04916a7 |
|
26-Feb-2015 |
gaurav rana <gaurav.rana@freescale.com> |
SECURE_BOOT : enable esbc_validate command for powerpc and arm platforms. esbc_validate command uses various IP Blocks: Security Monitor, CAAM block and SFP registers. Hence the respective CONFIG's are enabled. Apart from these CONFIG_SHA_PROG_HW_ACCEL and CONFIG_RSA are also enabled. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
b3f0f632 |
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12-Dec-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: Define PBI Flash Base for C29XPCIE Secure Boot CONFIG_SYS_PBI_FLASH_BASE is defined for Secure Boot on C29X Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
f6050790 |
|
24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/mpc85xx: Add T1024/T1023 SoC support Add support for Freescale T1024/T1023 SoC. The T1024 SoC includes the following function and features: - Two 64-bit Power architecture e5500 cores, up to 1.4GHz - private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC) - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration - Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI) - High-speed peripheral interfaces - Three PCI Express 2.0 controllers - Additional peripheral interfaces - One SATA 2.0 controller - Two USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/eSDHC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Two 8-channel DMA engines - Multicore programmable interrupt controller (PIC) - LCD interface (DIU) with 12 bit dual data rate - QUICC Engine block supporting TDM, HDLC, and UART - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T1024 and T1023: Feature T1024 T1023 QUICC Engine: yes no DIU: yes no Deep Sleep: yes no I2C controller: 4 3 DDR: 64-bit 32-bit IFC: 32-bit 28-bit Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e47c2a68 |
|
22-Apr-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080RDB Secure Boot Target is added for T2080RDB Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080RDB. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> |
#
40678159 |
|
22-Apr-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- secure boot target for t1040rdb T1040RDB.h file is removed and a unified file T104xRDB.h is created. Hence macro CONFIG_T1040 is renamed to CONFIG_T104x. Signed-off-by: Gaurav Kumar Rana <gaurav.rana@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> |
#
2d8db6d3 |
|
18-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T1040QDS and T1040RDB Secure Boot Target is added for T1040QDS and T1040RDB Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T1040QDS and CONFIG_T1040RDB Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
ca4819df |
|
18-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080QDS Secure Boot Target is added for T2080QDS Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080QDS. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
796a7810 |
|
18-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T4240QDS and T4160QDS Secure Boot Target is added for T4240QDS and T4160QDS Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T4240QDS. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
fb4a2409 |
|
18-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS Changes: 1. L2 cache is being invalidated by Boot ROM code for e6500 core. So removing the invalidation from start.S 2. Clear the LAW and corresponding configuration for CPC. Boot ROM code uses it as hosekeeping area. 3. For Secure boot, CPC is configured as SRAM and used as house keeping area. This configuration is to be disabled once in uboot. Earlier this disabling of CPC as SRAM was happening in cpu_init_r. As a result cache invalidation function was getting skipped in case CPC is configured as SRAM.This was causing random crashes. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
f978f7c2 |
|
11-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for BSC9132QDS Add NOR, SPI and SD secure boot targets for BSC9132QDS. Changes: - Debug TLB entry is not required for Secure Boot Target. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
0d2cff2d |
|
21-Aug-2013 |
Po Liu <po.liu@freescale.com> |
powerpc: add CONFIG_SECURE_BOOT condition into fsl_secure_boot.h This patch is for board config file not to add CONFIG_SECURE_BOOT condition for include the asm/fsl_secure_boot.h. Signed-off-by: Po Liu <Po.Liu@freescale.com> |
#
1a459660 |
|
08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
39bdaff4 |
|
25-Mar-2013 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
SECURE BOOT - Removed deletion of TLB entries code Boot ROM code creates TLB entries for 3.5G space before entering the u-boot. Earlier we were deleting these entries after early initialization of CPU. In recent past, code has been added to invalidate all these entries before relocation of u-boot code. So this code to delete TLB entries after CPU initialization is no longer required. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Acked-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
7065b7d4 |
|
15-Dec-2010 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
powerpc/p4080: Add support for secure boot flow Pre u-boot Flow: 1. User loads the u-boot image in flash 2. PBL/Configuration word is used to create LAW for Flash at 0xc0000000 (Please note that ISBC expects all these addresses, images to be validated, entry point etc within 0 - 3.5G range) 3. ISBC validates the u-boot image, and passes control to u-boot at 0xcffffffc. Changes in u-boot: 1. Temporarily map CONFIG_SYS_MONITOR_BASE to the 1M CONFIG_SYS_PBI_FLASH_WINDOW in AS=1. (The CONFIG_SYS_PBI_FLASH_WINDOW is the address map for the flash created by PBL/configuration word within 0 - 3.5G memory range. The u-boot image at this address has been validated by ISBC code) 2. Remove TLB entries for 0 - 3.5G created by ISBC code 3. Remove the LAW entry for the CONFIG_SYS_PBI_FLASH_WINDOW created by PBL/configuration word after switch to AS = 1 Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com> Acked-by: Wood Scott-B07421 <B07421@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
bef18454 |
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07-Nov-2019 |
Udit Agarwal <udit.agarwal@nxp.com> |
freescale/powerpc: Rename the config CONFIG_SECURE_BOOT name Rename the CONFIG_SECURE_BOOT name to CONFIG_NXP_ESBC to avoid conflicts with UEFI secure boot. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ea7971f7 |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_CMD_ESBC_VALIDATE to Kconfig This converts the following to Kconfig: CONFIG_CMD_ESBC_VALIDATE Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
089df18b |
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14-May-2017 |
Tom Rini <trini@konsulko.com> |
lib: move hash CONFIG options to Kconfig Commit 94e3c8c4fd7b ("crypto/fsl - Add progressive hashing support using hardware acceleration.") created entries for CONFIG_SHA1, CONFIG_SHA256, CONFIG_SHA_HW_ACCEL, and CONFIG_SHA_PROG_HW_ACCEL. However, no defconfig has migrated to it. Complete the move by first adding additional logic to various Kconfig files to select this when required and then use the moveconfig tool. In many cases we can select these because they are required to implement other drivers. We also correct how we include the various hashing algorithms in SPL. This commit was generated as follows (after Kconfig additions): [1] tools/moveconfig.py -y SHA1 SHA256 SHA_HW_ACCEL [2] tools/moveconfig.py -y SHA_PROG_HW_ACCEL Note: We cannot move SHA_HW_ACCEL and SHA_PROG_HW_ACCEL simultaneously because there is dependency between them. Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com> Cc: Naveen Burmi <NaveenBurmi@freescale.com> Cc: Po Liu <po.liu@freescale.com> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Priyanka Jain <Priyanka.Jain@freescale.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Chander Kashyap <k.chander@samsung.com> Cc: Steve Rae <steve.rae@raedomain.com> Cc: Dirk Eibach <eibach@gdsys.de> Cc: Feng Li <feng.li_2@nxp.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Sumit Garg <sumit.garg@nxp.com> Cc: Mingkai Hu <Mingkai.Hu@freescale.com> Cc: York Sun <york.sun@nxp.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Akshay Saraswat <akshay.s@samsung.com> Cc: Heiko Schocher <hs@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
c04b9b34 |
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26-Apr-2017 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_CMD_BLOB to Kconfig This converts the following to Kconfig: CONFIG_CMD_BLOB Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Add imply CMD_BLOB under CHAIN_OF_TRUST] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
0645c23a |
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30-Mar-2017 |
VINITHA PILLAI <vinitha.pillai@nxp.com> |
powerpc: T1042RDB: SECURE BOOT: Remove CONFIG_CMD_BLOB from SPL compilation BLOB feature is not required during SPL compilation. Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
28522678 |
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01-Mar-2017 |
Tom Rini <trini@konsulko.com> |
Freescale/NXP: Migrate CONFIG_FSL_CAAM to defconfigs In some cases this is absolutely required, so select this for some secure features. This also requires migration of RSA_FREESCALE_EXP Cc: Ruchika Gupta <ruchika.gupta@nxp.com> Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com> Cc: Naveen Burmi <NaveenBurmi@freescale.com> Cc: Po Liu <po.liu@freescale.com> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Priyanka Jain <Priyanka.Jain@freescale.com> Cc: Sumit Garg <sumit.garg@nxp.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Feng Li <feng.li_2@nxp.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Mingkai Hu <Mingkai.Hu@freescale.com> Cc: York Sun <york.sun@nxp.com> Cc: Saksham Jain <saksham.jain@nxp.freescale.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
88077715 |
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22-Jan-2017 |
Tom Rini <trini@konsulko.com> |
NXP: Introduce board/freescale/common/Kconfig and migrate CHAIN_OF_TRUST Introduce board/freescale/common/Kconfig so that we have a single place for CONFIG options that are shared between ARM and PowerPC NXP platforms. Cc: York Sun <york.sun@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3788b451 |
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21-Jan-2017 |
Jagan Teki <jagan@openedev.com> |
config: Move CONFIG_BOARD_LATE_INIT to defconfigs Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jagan@openedev.com> |
#
a1055038 |
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28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T104xQDS: Remove macro CONFIG_T104xD4QDS Remove this macro. It was added by e622d9ed but actually wasn't used. Signed-off-by: York Sun <york.sun@nxp.com> |
#
86e0a313 |
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28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T2080RDB: Remove macro CONFIG_T2080RDB Use TARGET_T2080RDB from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
80d26188 |
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28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T2080QDS: Remove macro T2080QDS Use TARGET_T2080QDS from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
f4f66940 |
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28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1040QDS: Remove macro CONFIG_T1040QDS Use TARGET_T1040QDS from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
673c01c7 |
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21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4240QDS: Remove macro CONFIG_T4240QDS Use CONFIG_TARGET_T4240QDS instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9c21d06c |
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21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4160QDS: Separate from T4240QDS in Kconfig Use TARGET_T4160QDS to simplify Kconfig options. Signed-off-by: York Sun <york.sun@nxp.com> |
#
78e56995 |
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21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T104xRDB: Remove macro CONFIG_T104xRDB and T104xD4RDB CONFIG_T104xRDB is defined in T104xRDB.h, so it is always enabled for all T1040RDB, T1040D4RDB, T1042RDB, T1042D4RDB, T1042RDB_PI. CONFIG_T104XD4RDB is defined for all T1040D4RDB, T1042D4RDB. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e5d5f5a8 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1024: Remove macro CONFIG_PPC_T1024 Replace CONFIG_PPC_T1024 with ARCH_T1024 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5ff3f41d |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1023: Remove macro CONFIG_PPC_T1023 Replace CONFIG_PPC_T1023 with ARCH_T1023 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
d46a4a13 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: B4860QDS: Remove macro CONFIG_B4860QDS Use CONFIG_TARGET_B4860QDS instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
95390360 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P5040: Remove macro CONFIG_P5040 Replace CONFIG_P5040 with ARCH_P5040 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
cefe11cd |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P5020: Remove macro CONFIG_PPC_P5020 Replace CONFIG_PPC_P5020 with ARCH_P5020 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e71372cb |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P4080: Remove macro CONFIG_PPC_P4080 Replace CONFIG_PPC_P4080 with ARCH_P4080 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5e5fdd2d |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P3041: Remove macro CONFIG_PPC_P3041 Replace CONFIG_PPC_P3041 with ARCH_P3041 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ce040c83 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P2041: Remove macro CONFIG_PPC_P2041 Replace CONFIG_PPC_P2041 with ARCH_P2041 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ebccf255 |
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16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: C29XPCIE: Remove macro CONFIG_C29XPCIE Use CONFIG_TARGET_C29XPCIE instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a202b9f8 |
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15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: BSC9132QDS: Remove CONFIG_BSC9132QDS macro Use CONFIG_TARGET_BSC9132QDS from Kconfig option, remove CONFIG_BSC9132QDS macro. Signed-off-by: York Sun <york.sun@nxp.com> |
#
d3662dff |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_SPL_DRIVERS_MISC_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d3e7e2b2 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_SPL_HASH_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
dbdaeee4 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_SPL_CRYPTO_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d3c1f467 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Move existing use of CONFIG_SPL_RSA to Kconfig A few boards define this in a header file which is incorrect. It means that Kconfig options that rely on this cannot be used. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3433a693 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Move existing use of CONFIG_SPL_DM to Kconfig A few boards define this in a header file which is incorrect. It means that Kconfig options that rely on this cannot be used. Move it. Note that quite a few boards defined this options but do not appear to actually use SPL: BSC9132QDS_NOR_DDRCLK100_SECURE BSC9132QDS_NOR_DDRCLK133_SECURE BSC9132QDS_SDCARD_DDRCLK100_SECURE BSC9132QDS_SDCARD_DDRCLK133_SECURE BSC9132QDS_SPIFLASH_DDRCLK100_SECURE BSC9132QDS_SPIFLASH_DDRCLK133_SECURE C29XPCIE_NOR_SECBOOT P1010RDB-PA_36BIT_NAND_SECBOOT P1010RDB-PA_36BIT_SPIFLASH_SECBOOT P1010RDB-PA_NAND_SECBOOT P1010RDB-PA_NOR_SECBOOT P1010RDB-PB_36BIT_NOR_SECBOOT P1010RDB-PB_36BIT_SPIFLASH_SECBOOT P1010RDB-PB_NAND_SECBOOT P1010RDB-PB_NOR_SECBOOT P3041DS_SECURE_BOOT P4080DS_SECURE_BOOT P5020DS_NAND_SECURE_BOOT P5040DS_SECURE_BOOT T1023RDB_SECURE_BOOT T1024QDS_DDR4_SECURE_BOOT T1024QDS_SECURE_BOOT T1024RDB_SECURE_BOOT T1040RDB_SECURE_BOOT T1042D4RDB_SECURE_BOOT T1042RDB_SECURE_BOOT T2080QDS_SECURE_BOOT T2080RDB_SECURE_BOOT T4160QDS_SECURE_BOOT T4240QDS_SECURE_BOOT ls1021aqds_nor_SECURE_BOOT ls1021atwr_nor_SECURE_BOOT ls1043ardb_SECURE_BOOT For these boards CONFIG_SPL_DM will no-longer be defined in SPL. But since they apparently don't have an SPL, this should not matter. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
b63f8a43 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
arm: fsl: Adjust ordering of #ifndef CONFIG_SPL_BUILD The secure boot header files incorrectly define SPL options only if CONFIG_SPL_BUILD is defined. This means that the options are only enabled in an SPL build, and not with a normal 'make xxx_defconfig'. This means that moveconfig.py cannot work, since it sees the options as disabled even when they may be manually enabled in an SPL build. Fix this by changing the order. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
69d4b48c |
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14-Jun-2016 |
Sumit Garg <sumit.garg@nxp.com> |
SECURE_BOOT: Enable SD as a source for bootscript Add support for reading bootscript and bootscript header from SD. Also renamed macros *_FLASH to *_DEVICE to represent SD alongwith NAND and NOR flash. Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
aa36c84e |
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13-Jul-2016 |
Sumit Garg <sumit.garg@nxp.com> |
powerpc/mpc85xx: T104x: Add nand secure boot target For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In non-secure boot scenario from NAND, this address will map to CPC configured as SRAM. But in case of secure boot, this default address always maps to IBR (Internal Boot ROM). The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. For secure boot target from NAND, the text base for SPL is kept same as non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000) As a the virtual and physical address of CPC would be different. The virtual address 0xFFFx_xxxx needs to be mapped to physical address 0xBFFx_xxxx. Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000 and update DCFG SCRTACH1 register with location of Header required for secure boot. The changes are similar to commit 467a40dfe35f48d830f01a72617207d03ca85b4d powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC is only 256K and thus SPL framework is used. The changes are only applicable for SPL U-Boot running out of CPC SRAM and not the next level U-Boot loaded on DDR. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
8f01397b |
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13-Jul-2016 |
Sumit Garg <sumit.garg@nxp.com> |
powerpc/mpc85xx: SECURE BOOT- Enable chain of trust in SPL As part of Chain of Trust for Secure boot, the SPL U-Boot will validate the next level U-boot image. Add a new function spl_validate_uboot to perform the validation. Enable hardware crypto operations in SPL using SEC block. In case of Secure Boot, PAMU is not bypassed. For allowing SEC block access to CPC configured as SRAM, configure PAMU. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
73223f0e |
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22-Feb-2016 |
Simon Glass <sjg@chromium.org> |
Kconfig: Move CONFIG_FIT and related options to Kconfig There are already two FIT options in Kconfig but the CONFIG options are still in the header files. We need to do a proper move to fix this. Move these options to Kconfig and tidy up board configuration: CONFIG_FIT CONFIG_OF_BOARD_SETUP CONFIG_OF_SYSTEM_SETUP CONFIG_FIT_SIGNATURE CONFIG_FIT_BEST_MATCH CONFIG_FIT_VERBOSE CONFIG_OF_STDOUT_VIA_ALIAS CONFIG_RSA Unfortunately the first one is a little complicated. We need to make sure this option is not enabled in SPL by this change. Also this option is enabled automatically in the host builds by defining CONFIG_FIT in the image.h file. To solve this, add a new IMAGE_USE_FIT #define which can be used in files that are built on the host but must also build for U-Boot and SPL. Note: Masahiro's moveconfig.py script is amazing. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Add microblaze change, various configs/ re-applies] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
9e971632 |
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22-Feb-2016 |
Simon Glass <sjg@chromium.org> |
freescale: Remove CONFIG_DM from header files Kconfig options must defined in the defconfig files. Since RSA_SOFTWARE_EXP relies on CONFIG_DM, unless it is set in kconfig we cannot enable RSA. Remove the hacks which enable CONFIG_DM in header files and update the defconfig. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d0a6d7ce |
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22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: enable chain of trust for PowerPC platforms Chain of Trust is enabled for PowerPC platforms for Secure Boot. CONFIG_BOARD_LATE_INIT is defined. In board_late_init(), fsl_setenv_chain_of_trust() is called which will perform the following: - If boot mode is non-secure, return (No Change) - If boot mode is secure, set the following environmet variables: bootdelay = 0 (To disable Boot Prompt) bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
bdc22074 |
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22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: split the secure boot functionality in two parts There are two phases in Secure Boot 1. ISBC: In BootROM, validate the BootLoader (U-Boot). 2. ESBC: In U-Boot, continuing the Chain of Trust by validating and booting LINUX. For ESBC phase, there is no difference in SoC's based on ARM or PowerPC cores. But the exit conditions after ISBC phase i.e. entry conditions for U-Boot are different for ARM and PowerPC. PowerPC: If Secure Boot is executed, a separate U-Boot target is required which must be compiled with a diffrent Text Base as compared to Non-Secure Boot. There are some LAW and TLB settings which are required specifically for Secure Boot scenario. ARM: ARM based SoC's have a fixed memory map and exit conditions from BootROM are same irrespective of boot mode (Secure or Non-Secure). Thus the current Secure Boot functionlity has been split into two parts: CONFIG_CHAIN_OF_TRUST This will have the following functionality as part of U-Boot: 1. Enable commands like esbc_validate, esbc_halt 2. Change the environment settings based on bootmode, determined at run time: - If bootmode is non-secure, no change - If bootmode is secure, set the following: - bootdelay = 0 (Don't give boot prompt) - bootcmd = Validate and execute the bootscript. CONFIG_SECURE_BOOT This is defined only for creating a different compile time target for secure boot. Traditionally, both these functionalities were defined under CONFIG_SECURE_BOOT. This patch is aimed at removing the requirement for a separate Secure Boot target for ARM based SoC's. CONFIG_CHAIN_OF_TRUST will be defined and boot mode will be determine at run time. Another Security Requirement for running CHAIN_OF_TRUST is that U-Boot environemnt must not be picked from flash/external memory. This cannot be done based on bootmode at run time in current U-Boot architecture. Once this dependency is resolved, no separate SECURE_BOOT target will be required for ARM based SoC's. Currently, the only code under CONFIG_SECURE_BOOT for ARM SoC's is defining CONFIG_ENV_IS_NOWHERE Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
74eecd82 |
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22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: include/configs: move definition of CONFIG_CMD_BLOB CONFIG_CMD_BLOB must be defined in case of Secure Boot. It was earlier defined in all config files. The definition has been moved to a common file which is included by all configs. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
2ed948f4 |
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31-Jul-2015 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
SECURE_BOOT: Disable IE Key feature for RAMBOOT ISBC Key Extension feature is not applicable for RAMBOOT as there is no way to retrieve the CSF Header and validated IE Key table from SRAM once CPC has been disabled. The feature is only applicable in case of NOR SECURE BOOT. Code Cleanup: The SECURE_BOOT specific defines have been moved from arch-ls102xa/config.h to arm/include/asm/fsl_secure_boot.h Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
5050f6f0 |
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15-Jun-2015 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT-Copy Boot Script on RAM For running Chain of Trust when doing Secure Boot from NAND, the Bootscript header and bootscript must be copied from NAND to RAM(DDR). The addresses and commands for the same have been defined. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
467a40df |
|
15-Jun-2015 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 Secure Boot Target is added for NAND for P3041. For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In case of secure boot, this default address maps to Boot ROM. The Boot ROM code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is configured as SRAM. U-Boot binary will be located on SRAM configured at address 0xBFF00000. In the U-Boot code, TLB entries are created to map the virtual address 0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e622d9ed |
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26-Mar-2015 |
gaurav rana <gaurav.rana@freescale.com> |
powerpc/T104xD4: Add Secure boot support for T104xD4RDB platforms defconfig files are added and SFP version for these platforms is updated. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
98cb0efd |
|
10-Mar-2015 |
gaurav rana <gaurav.rana@freescale.com> |
Add bootscript support to esbc_validate. 1. Default environment will be used for secure boot flow which can't be edited or saved. 2. Command for secure boot is predefined in the default environment which will run on autoboot (and autoboot is the only option allowed in case of secure boot) and it looks like this: #define CONFIG_SECBOOT \ "setenv bs_hdraddr 0xe8e00000;" \ "esbc_validate $bs_hdraddr;" \ "source $img_addr;" \ "esbc_halt;" #endif 3. Boot Script can contain esbc_validate commands and bootm command. Uboot source command used in default secure boot command will run the bootscript. 4. Command esbc_halt added to ensure either bootm executes after validation of images or core should just spin. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e04916a7 |
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26-Feb-2015 |
gaurav rana <gaurav.rana@freescale.com> |
SECURE_BOOT : enable esbc_validate command for powerpc and arm platforms. esbc_validate command uses various IP Blocks: Security Monitor, CAAM block and SFP registers. Hence the respective CONFIG's are enabled. Apart from these CONFIG_SHA_PROG_HW_ACCEL and CONFIG_RSA are also enabled. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
b3f0f632 |
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12-Dec-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: Define PBI Flash Base for C29XPCIE Secure Boot CONFIG_SYS_PBI_FLASH_BASE is defined for Secure Boot on C29X Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
f6050790 |
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24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/mpc85xx: Add T1024/T1023 SoC support Add support for Freescale T1024/T1023 SoC. The T1024 SoC includes the following function and features: - Two 64-bit Power architecture e5500 cores, up to 1.4GHz - private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC) - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration - Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI) - High-speed peripheral interfaces - Three PCI Express 2.0 controllers - Additional peripheral interfaces - One SATA 2.0 controller - Two USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/eSDHC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Two 8-channel DMA engines - Multicore programmable interrupt controller (PIC) - LCD interface (DIU) with 12 bit dual data rate - QUICC Engine block supporting TDM, HDLC, and UART - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T1024 and T1023: Feature T1024 T1023 QUICC Engine: yes no DIU: yes no Deep Sleep: yes no I2C controller: 4 3 DDR: 64-bit 32-bit IFC: 32-bit 28-bit Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e47c2a68 |
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22-Apr-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080RDB Secure Boot Target is added for T2080RDB Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080RDB. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> |
#
40678159 |
|
22-Apr-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- secure boot target for t1040rdb T1040RDB.h file is removed and a unified file T104xRDB.h is created. Hence macro CONFIG_T1040 is renamed to CONFIG_T104x. Signed-off-by: Gaurav Kumar Rana <gaurav.rana@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> |
#
2d8db6d3 |
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18-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T1040QDS and T1040RDB Secure Boot Target is added for T1040QDS and T1040RDB Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T1040QDS and CONFIG_T1040RDB Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
ca4819df |
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18-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080QDS Secure Boot Target is added for T2080QDS Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080QDS. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
796a7810 |
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18-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T4240QDS and T4160QDS Secure Boot Target is added for T4240QDS and T4160QDS Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T4240QDS. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
fb4a2409 |
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18-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS Changes: 1. L2 cache is being invalidated by Boot ROM code for e6500 core. So removing the invalidation from start.S 2. Clear the LAW and corresponding configuration for CPC. Boot ROM code uses it as hosekeeping area. 3. For Secure boot, CPC is configured as SRAM and used as house keeping area. This configuration is to be disabled once in uboot. Earlier this disabling of CPC as SRAM was happening in cpu_init_r. As a result cache invalidation function was getting skipped in case CPC is configured as SRAM.This was causing random crashes. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
f978f7c2 |
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11-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for BSC9132QDS Add NOR, SPI and SD secure boot targets for BSC9132QDS. Changes: - Debug TLB entry is not required for Secure Boot Target. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
0d2cff2d |
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21-Aug-2013 |
Po Liu <po.liu@freescale.com> |
powerpc: add CONFIG_SECURE_BOOT condition into fsl_secure_boot.h This patch is for board config file not to add CONFIG_SECURE_BOOT condition for include the asm/fsl_secure_boot.h. Signed-off-by: Po Liu <Po.Liu@freescale.com> |
#
1a459660 |
|
08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
39bdaff4 |
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25-Mar-2013 |
Ruchika Gupta <ruchika.gupta@freescale.com> |
SECURE BOOT - Removed deletion of TLB entries code Boot ROM code creates TLB entries for 3.5G space before entering the u-boot. Earlier we were deleting these entries after early initialization of CPU. In recent past, code has been added to invalidate all these entries before relocation of u-boot code. So this code to delete TLB entries after CPU initialization is no longer required. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Acked-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
7065b7d4 |
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15-Dec-2010 |
Ruchika Gupta <ruchika.gupta@freescale.com> |
powerpc/p4080: Add support for secure boot flow Pre u-boot Flow: 1. User loads the u-boot image in flash 2. PBL/Configuration word is used to create LAW for Flash at 0xc0000000 (Please note that ISBC expects all these addresses, images to be validated, entry point etc within 0 - 3.5G range) 3. ISBC validates the u-boot image, and passes control to u-boot at 0xcffffffc. Changes in u-boot: 1. Temporarily map CONFIG_SYS_MONITOR_BASE to the 1M CONFIG_SYS_PBI_FLASH_WINDOW in AS=1. (The CONFIG_SYS_PBI_FLASH_WINDOW is the address map for the flash created by PBL/configuration word within 0 - 3.5G memory range. The u-boot image at this address has been validated by ISBC code) 2. Remove TLB entries for 0 - 3.5G created by ISBC code 3. Remove the LAW entry for the CONFIG_SYS_PBI_FLASH_WINDOW created by PBL/configuration word after switch to AS = 1 Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com> Acked-by: Wood Scott-B07421 <B07421@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
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#
ea7971f7 |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_CMD_ESBC_VALIDATE to Kconfig This converts the following to Kconfig: CONFIG_CMD_ESBC_VALIDATE Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
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#
089df18b |
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14-May-2017 |
Tom Rini <trini@konsulko.com> |
lib: move hash CONFIG options to Kconfig Commit 94e3c8c4fd7b ("crypto/fsl - Add progressive hashing support using hardware acceleration.") created entries for CONFIG_SHA1, CONFIG_SHA256, CONFIG_SHA_HW_ACCEL, and CONFIG_SHA_PROG_HW_ACCEL. However, no defconfig has migrated to it. Complete the move by first adding additional logic to various Kconfig files to select this when required and then use the moveconfig tool. In many cases we can select these because they are required to implement other drivers. We also correct how we include the various hashing algorithms in SPL. This commit was generated as follows (after Kconfig additions): [1] tools/moveconfig.py -y SHA1 SHA256 SHA_HW_ACCEL [2] tools/moveconfig.py -y SHA_PROG_HW_ACCEL Note: We cannot move SHA_HW_ACCEL and SHA_PROG_HW_ACCEL simultaneously because there is dependency between them. Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com> Cc: Naveen Burmi <NaveenBurmi@freescale.com> Cc: Po Liu <po.liu@freescale.com> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Priyanka Jain <Priyanka.Jain@freescale.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Chander Kashyap <k.chander@samsung.com> Cc: Steve Rae <steve.rae@raedomain.com> Cc: Dirk Eibach <eibach@gdsys.de> Cc: Feng Li <feng.li_2@nxp.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Sumit Garg <sumit.garg@nxp.com> Cc: Mingkai Hu <Mingkai.Hu@freescale.com> Cc: York Sun <york.sun@nxp.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Akshay Saraswat <akshay.s@samsung.com> Cc: Heiko Schocher <hs@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
c04b9b34 |
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26-Apr-2017 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_CMD_BLOB to Kconfig This converts the following to Kconfig: CONFIG_CMD_BLOB Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Add imply CMD_BLOB under CHAIN_OF_TRUST] Signed-off-by: Tom Rini <trini@konsulko.com>
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#
0645c23a |
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30-Mar-2017 |
VINITHA PILLAI <vinitha.pillai@nxp.com> |
powerpc: T1042RDB: SECURE BOOT: Remove CONFIG_CMD_BLOB from SPL compilation BLOB feature is not required during SPL compilation. Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
28522678 |
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01-Mar-2017 |
Tom Rini <trini@konsulko.com> |
Freescale/NXP: Migrate CONFIG_FSL_CAAM to defconfigs In some cases this is absolutely required, so select this for some secure features. This also requires migration of RSA_FREESCALE_EXP Cc: Ruchika Gupta <ruchika.gupta@nxp.com> Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com> Cc: Naveen Burmi <NaveenBurmi@freescale.com> Cc: Po Liu <po.liu@freescale.com> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Priyanka Jain <Priyanka.Jain@freescale.com> Cc: Sumit Garg <sumit.garg@nxp.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Feng Li <feng.li_2@nxp.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Mingkai Hu <Mingkai.Hu@freescale.com> Cc: York Sun <york.sun@nxp.com> Cc: Saksham Jain <saksham.jain@nxp.freescale.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
88077715 |
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22-Jan-2017 |
Tom Rini <trini@konsulko.com> |
NXP: Introduce board/freescale/common/Kconfig and migrate CHAIN_OF_TRUST Introduce board/freescale/common/Kconfig so that we have a single place for CONFIG options that are shared between ARM and PowerPC NXP platforms. Cc: York Sun <york.sun@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
3788b451 |
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21-Jan-2017 |
Jagan Teki <jagan@openedev.com> |
config: Move CONFIG_BOARD_LATE_INIT to defconfigs Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jagan@openedev.com>
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#
a1055038 |
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28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T104xQDS: Remove macro CONFIG_T104xD4QDS Remove this macro. It was added by e622d9ed but actually wasn't used. Signed-off-by: York Sun <york.sun@nxp.com>
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#
86e0a313 |
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28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T2080RDB: Remove macro CONFIG_T2080RDB Use TARGET_T2080RDB from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com>
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#
80d26188 |
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28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T2080QDS: Remove macro T2080QDS Use TARGET_T2080QDS from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com>
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#
f4f66940 |
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28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1040QDS: Remove macro CONFIG_T1040QDS Use TARGET_T1040QDS from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com>
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#
673c01c7 |
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21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4240QDS: Remove macro CONFIG_T4240QDS Use CONFIG_TARGET_T4240QDS instead. Signed-off-by: York Sun <york.sun@nxp.com>
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#
9c21d06c |
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21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4160QDS: Separate from T4240QDS in Kconfig Use TARGET_T4160QDS to simplify Kconfig options. Signed-off-by: York Sun <york.sun@nxp.com>
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#
78e56995 |
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21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T104xRDB: Remove macro CONFIG_T104xRDB and T104xD4RDB CONFIG_T104xRDB is defined in T104xRDB.h, so it is always enabled for all T1040RDB, T1040D4RDB, T1042RDB, T1042D4RDB, T1042RDB_PI. CONFIG_T104XD4RDB is defined for all T1040D4RDB, T1042D4RDB. Signed-off-by: York Sun <york.sun@nxp.com>
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#
e5d5f5a8 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1024: Remove macro CONFIG_PPC_T1024 Replace CONFIG_PPC_T1024 with ARCH_T1024 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
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#
5ff3f41d |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1023: Remove macro CONFIG_PPC_T1023 Replace CONFIG_PPC_T1023 with ARCH_T1023 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
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#
d46a4a13 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: B4860QDS: Remove macro CONFIG_B4860QDS Use CONFIG_TARGET_B4860QDS instead. Signed-off-by: York Sun <york.sun@nxp.com>
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#
95390360 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P5040: Remove macro CONFIG_P5040 Replace CONFIG_P5040 with ARCH_P5040 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
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#
cefe11cd |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P5020: Remove macro CONFIG_PPC_P5020 Replace CONFIG_PPC_P5020 with ARCH_P5020 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
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#
e71372cb |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P4080: Remove macro CONFIG_PPC_P4080 Replace CONFIG_PPC_P4080 with ARCH_P4080 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
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#
5e5fdd2d |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P3041: Remove macro CONFIG_PPC_P3041 Replace CONFIG_PPC_P3041 with ARCH_P3041 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
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#
ce040c83 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P2041: Remove macro CONFIG_PPC_P2041 Replace CONFIG_PPC_P2041 with ARCH_P2041 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
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#
ebccf255 |
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16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: C29XPCIE: Remove macro CONFIG_C29XPCIE Use CONFIG_TARGET_C29XPCIE instead. Signed-off-by: York Sun <york.sun@nxp.com>
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#
a202b9f8 |
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15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: BSC9132QDS: Remove CONFIG_BSC9132QDS macro Use CONFIG_TARGET_BSC9132QDS from Kconfig option, remove CONFIG_BSC9132QDS macro. Signed-off-by: York Sun <york.sun@nxp.com>
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#
d3662dff |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_SPL_DRIVERS_MISC_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d3e7e2b2 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_SPL_HASH_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
dbdaeee4 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_SPL_CRYPTO_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
d3c1f467 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Move existing use of CONFIG_SPL_RSA to Kconfig A few boards define this in a header file which is incorrect. It means that Kconfig options that rely on this cannot be used. Move it. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
3433a693 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
Move existing use of CONFIG_SPL_DM to Kconfig A few boards define this in a header file which is incorrect. It means that Kconfig options that rely on this cannot be used. Move it. Note that quite a few boards defined this options but do not appear to actually use SPL: BSC9132QDS_NOR_DDRCLK100_SECURE BSC9132QDS_NOR_DDRCLK133_SECURE BSC9132QDS_SDCARD_DDRCLK100_SECURE BSC9132QDS_SDCARD_DDRCLK133_SECURE BSC9132QDS_SPIFLASH_DDRCLK100_SECURE BSC9132QDS_SPIFLASH_DDRCLK133_SECURE C29XPCIE_NOR_SECBOOT P1010RDB-PA_36BIT_NAND_SECBOOT P1010RDB-PA_36BIT_SPIFLASH_SECBOOT P1010RDB-PA_NAND_SECBOOT P1010RDB-PA_NOR_SECBOOT P1010RDB-PB_36BIT_NOR_SECBOOT P1010RDB-PB_36BIT_SPIFLASH_SECBOOT P1010RDB-PB_NAND_SECBOOT P1010RDB-PB_NOR_SECBOOT P3041DS_SECURE_BOOT P4080DS_SECURE_BOOT P5020DS_NAND_SECURE_BOOT P5040DS_SECURE_BOOT T1023RDB_SECURE_BOOT T1024QDS_DDR4_SECURE_BOOT T1024QDS_SECURE_BOOT T1024RDB_SECURE_BOOT T1040RDB_SECURE_BOOT T1042D4RDB_SECURE_BOOT T1042RDB_SECURE_BOOT T2080QDS_SECURE_BOOT T2080RDB_SECURE_BOOT T4160QDS_SECURE_BOOT T4240QDS_SECURE_BOOT ls1021aqds_nor_SECURE_BOOT ls1021atwr_nor_SECURE_BOOT ls1043ardb_SECURE_BOOT For these boards CONFIG_SPL_DM will no-longer be defined in SPL. But since they apparently don't have an SPL, this should not matter. Signed-off-by: Simon Glass <sjg@chromium.org>
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b63f8a43 |
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12-Sep-2016 |
Simon Glass <sjg@chromium.org> |
arm: fsl: Adjust ordering of #ifndef CONFIG_SPL_BUILD The secure boot header files incorrectly define SPL options only if CONFIG_SPL_BUILD is defined. This means that the options are only enabled in an SPL build, and not with a normal 'make xxx_defconfig'. This means that moveconfig.py cannot work, since it sees the options as disabled even when they may be manually enabled in an SPL build. Fix this by changing the order. Signed-off-by: Simon Glass <sjg@chromium.org>
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69d4b48c |
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14-Jun-2016 |
Sumit Garg <sumit.garg@nxp.com> |
SECURE_BOOT: Enable SD as a source for bootscript Add support for reading bootscript and bootscript header from SD. Also renamed macros *_FLASH to *_DEVICE to represent SD alongwith NAND and NOR flash. Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
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aa36c84e |
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13-Jul-2016 |
Sumit Garg <sumit.garg@nxp.com> |
powerpc/mpc85xx: T104x: Add nand secure boot target For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In non-secure boot scenario from NAND, this address will map to CPC configured as SRAM. But in case of secure boot, this default address always maps to IBR (Internal Boot ROM). The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. For secure boot target from NAND, the text base for SPL is kept same as non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000) As a the virtual and physical address of CPC would be different. The virtual address 0xFFFx_xxxx needs to be mapped to physical address 0xBFFx_xxxx. Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000 and update DCFG SCRTACH1 register with location of Header required for secure boot. The changes are similar to commit 467a40dfe35f48d830f01a72617207d03ca85b4d powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC is only 256K and thus SPL framework is used. The changes are only applicable for SPL U-Boot running out of CPC SRAM and not the next level U-Boot loaded on DDR. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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8f01397b |
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13-Jul-2016 |
Sumit Garg <sumit.garg@nxp.com> |
powerpc/mpc85xx: SECURE BOOT- Enable chain of trust in SPL As part of Chain of Trust for Secure boot, the SPL U-Boot will validate the next level U-boot image. Add a new function spl_validate_uboot to perform the validation. Enable hardware crypto operations in SPL using SEC block. In case of Secure Boot, PAMU is not bypassed. For allowing SEC block access to CPC configured as SRAM, configure PAMU. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
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73223f0e |
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22-Feb-2016 |
Simon Glass <sjg@chromium.org> |
Kconfig: Move CONFIG_FIT and related options to Kconfig There are already two FIT options in Kconfig but the CONFIG options are still in the header files. We need to do a proper move to fix this. Move these options to Kconfig and tidy up board configuration: CONFIG_FIT CONFIG_OF_BOARD_SETUP CONFIG_OF_SYSTEM_SETUP CONFIG_FIT_SIGNATURE CONFIG_FIT_BEST_MATCH CONFIG_FIT_VERBOSE CONFIG_OF_STDOUT_VIA_ALIAS CONFIG_RSA Unfortunately the first one is a little complicated. We need to make sure this option is not enabled in SPL by this change. Also this option is enabled automatically in the host builds by defining CONFIG_FIT in the image.h file. To solve this, add a new IMAGE_USE_FIT #define which can be used in files that are built on the host but must also build for U-Boot and SPL. Note: Masahiro's moveconfig.py script is amazing. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Add microblaze change, various configs/ re-applies] Signed-off-by: Tom Rini <trini@konsulko.com>
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9e971632 |
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22-Feb-2016 |
Simon Glass <sjg@chromium.org> |
freescale: Remove CONFIG_DM from header files Kconfig options must defined in the defconfig files. Since RSA_SOFTWARE_EXP relies on CONFIG_DM, unless it is set in kconfig we cannot enable RSA. Remove the hacks which enable CONFIG_DM in header files and update the defconfig. Signed-off-by: Simon Glass <sjg@chromium.org>
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d0a6d7ce |
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22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: enable chain of trust for PowerPC platforms Chain of Trust is enabled for PowerPC platforms for Secure Boot. CONFIG_BOARD_LATE_INIT is defined. In board_late_init(), fsl_setenv_chain_of_trust() is called which will perform the following: - If boot mode is non-secure, return (No Change) - If boot mode is secure, set the following environmet variables: bootdelay = 0 (To disable Boot Prompt) bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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bdc22074 |
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22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: split the secure boot functionality in two parts There are two phases in Secure Boot 1. ISBC: In BootROM, validate the BootLoader (U-Boot). 2. ESBC: In U-Boot, continuing the Chain of Trust by validating and booting LINUX. For ESBC phase, there is no difference in SoC's based on ARM or PowerPC cores. But the exit conditions after ISBC phase i.e. entry conditions for U-Boot are different for ARM and PowerPC. PowerPC: If Secure Boot is executed, a separate U-Boot target is required which must be compiled with a diffrent Text Base as compared to Non-Secure Boot. There are some LAW and TLB settings which are required specifically for Secure Boot scenario. ARM: ARM based SoC's have a fixed memory map and exit conditions from BootROM are same irrespective of boot mode (Secure or Non-Secure). Thus the current Secure Boot functionlity has been split into two parts: CONFIG_CHAIN_OF_TRUST This will have the following functionality as part of U-Boot: 1. Enable commands like esbc_validate, esbc_halt 2. Change the environment settings based on bootmode, determined at run time: - If bootmode is non-secure, no change - If bootmode is secure, set the following: - bootdelay = 0 (Don't give boot prompt) - bootcmd = Validate and execute the bootscript. CONFIG_SECURE_BOOT This is defined only for creating a different compile time target for secure boot. Traditionally, both these functionalities were defined under CONFIG_SECURE_BOOT. This patch is aimed at removing the requirement for a separate Secure Boot target for ARM based SoC's. CONFIG_CHAIN_OF_TRUST will be defined and boot mode will be determine at run time. Another Security Requirement for running CHAIN_OF_TRUST is that U-Boot environemnt must not be picked from flash/external memory. This cannot be done based on bootmode at run time in current U-Boot architecture. Once this dependency is resolved, no separate SECURE_BOOT target will be required for ARM based SoC's. Currently, the only code under CONFIG_SECURE_BOOT for ARM SoC's is defining CONFIG_ENV_IS_NOWHERE Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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74eecd82 |
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22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: include/configs: move definition of CONFIG_CMD_BLOB CONFIG_CMD_BLOB must be defined in case of Secure Boot. It was earlier defined in all config files. The definition has been moved to a common file which is included by all configs. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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2ed948f4 |
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31-Jul-2015 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
SECURE_BOOT: Disable IE Key feature for RAMBOOT ISBC Key Extension feature is not applicable for RAMBOOT as there is no way to retrieve the CSF Header and validated IE Key table from SRAM once CPC has been disabled. The feature is only applicable in case of NOR SECURE BOOT. Code Cleanup: The SECURE_BOOT specific defines have been moved from arch-ls102xa/config.h to arm/include/asm/fsl_secure_boot.h Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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5050f6f0 |
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15-Jun-2015 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT-Copy Boot Script on RAM For running Chain of Trust when doing Secure Boot from NAND, the Bootscript header and bootscript must be copied from NAND to RAM(DDR). The addresses and commands for the same have been defined. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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467a40df |
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15-Jun-2015 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 Secure Boot Target is added for NAND for P3041. For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In case of secure boot, this default address maps to Boot ROM. The Boot ROM code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is configured as SRAM. U-Boot binary will be located on SRAM configured at address 0xBFF00000. In the U-Boot code, TLB entries are created to map the virtual address 0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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e622d9ed |
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26-Mar-2015 |
gaurav rana <gaurav.rana@freescale.com> |
powerpc/T104xD4: Add Secure boot support for T104xD4RDB platforms defconfig files are added and SFP version for these platforms is updated. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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98cb0efd |
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10-Mar-2015 |
gaurav rana <gaurav.rana@freescale.com> |
Add bootscript support to esbc_validate. 1. Default environment will be used for secure boot flow which can't be edited or saved. 2. Command for secure boot is predefined in the default environment which will run on autoboot (and autoboot is the only option allowed in case of secure boot) and it looks like this: #define CONFIG_SECBOOT \ "setenv bs_hdraddr 0xe8e00000;" \ "esbc_validate $bs_hdraddr;" \ "source $img_addr;" \ "esbc_halt;" #endif 3. Boot Script can contain esbc_validate commands and bootm command. Uboot source command used in default secure boot command will run the bootscript. 4. Command esbc_halt added to ensure either bootm executes after validation of images or core should just spin. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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e04916a7 |
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26-Feb-2015 |
gaurav rana <gaurav.rana@freescale.com> |
SECURE_BOOT : enable esbc_validate command for powerpc and arm platforms. esbc_validate command uses various IP Blocks: Security Monitor, CAAM block and SFP registers. Hence the respective CONFIG's are enabled. Apart from these CONFIG_SHA_PROG_HW_ACCEL and CONFIG_RSA are also enabled. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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b3f0f632 |
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12-Dec-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: Define PBI Flash Base for C29XPCIE Secure Boot CONFIG_SYS_PBI_FLASH_BASE is defined for Secure Boot on C29X Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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f6050790 |
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24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/mpc85xx: Add T1024/T1023 SoC support Add support for Freescale T1024/T1023 SoC. The T1024 SoC includes the following function and features: - Two 64-bit Power architecture e5500 cores, up to 1.4GHz - private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC) - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration - Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI) - High-speed peripheral interfaces - Three PCI Express 2.0 controllers - Additional peripheral interfaces - One SATA 2.0 controller - Two USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/eSDHC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Two 8-channel DMA engines - Multicore programmable interrupt controller (PIC) - LCD interface (DIU) with 12 bit dual data rate - QUICC Engine block supporting TDM, HDLC, and UART - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T1024 and T1023: Feature T1024 T1023 QUICC Engine: yes no DIU: yes no Deep Sleep: yes no I2C controller: 4 3 DDR: 64-bit 32-bit IFC: 32-bit 28-bit Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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e47c2a68 |
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22-Apr-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080RDB Secure Boot Target is added for T2080RDB Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080RDB. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
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40678159 |
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22-Apr-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- secure boot target for t1040rdb T1040RDB.h file is removed and a unified file T104xRDB.h is created. Hence macro CONFIG_T1040 is renamed to CONFIG_T104x. Signed-off-by: Gaurav Kumar Rana <gaurav.rana@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
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2d8db6d3 |
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18-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T1040QDS and T1040RDB Secure Boot Target is added for T1040QDS and T1040RDB Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T1040QDS and CONFIG_T1040RDB Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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ca4819df |
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18-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080QDS Secure Boot Target is added for T2080QDS Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080QDS. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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796a7810 |
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18-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T4240QDS and T4160QDS Secure Boot Target is added for T4240QDS and T4160QDS Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T4240QDS. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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fb4a2409 |
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18-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS Changes: 1. L2 cache is being invalidated by Boot ROM code for e6500 core. So removing the invalidation from start.S 2. Clear the LAW and corresponding configuration for CPC. Boot ROM code uses it as hosekeeping area. 3. For Secure boot, CPC is configured as SRAM and used as house keeping area. This configuration is to be disabled once in uboot. Earlier this disabling of CPC as SRAM was happening in cpu_init_r. As a result cache invalidation function was getting skipped in case CPC is configured as SRAM.This was causing random crashes. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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f978f7c2 |
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11-Mar-2014 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for BSC9132QDS Add NOR, SPI and SD secure boot targets for BSC9132QDS. Changes: - Debug TLB entry is not required for Secure Boot Target. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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0d2cff2d |
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21-Aug-2013 |
Po Liu <po.liu@freescale.com> |
powerpc: add CONFIG_SECURE_BOOT condition into fsl_secure_boot.h This patch is for board config file not to add CONFIG_SECURE_BOOT condition for include the asm/fsl_secure_boot.h. Signed-off-by: Po Liu <Po.Liu@freescale.com>
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1a459660 |
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08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
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39bdaff4 |
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25-Mar-2013 |
Ruchika Gupta <ruchika.gupta@freescale.com> |
SECURE BOOT - Removed deletion of TLB entries code Boot ROM code creates TLB entries for 3.5G space before entering the u-boot. Earlier we were deleting these entries after early initialization of CPU. In recent past, code has been added to invalidate all these entries before relocation of u-boot code. So this code to delete TLB entries after CPU initialization is no longer required. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Acked-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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7065b7d4 |
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15-Dec-2010 |
Ruchika Gupta <ruchika.gupta@freescale.com> |
powerpc/p4080: Add support for secure boot flow Pre u-boot Flow: 1. User loads the u-boot image in flash 2. PBL/Configuration word is used to create LAW for Flash at 0xc0000000 (Please note that ISBC expects all these addresses, images to be validated, entry point etc within 0 - 3.5G range) 3. ISBC validates the u-boot image, and passes control to u-boot at 0xcffffffc. Changes in u-boot: 1. Temporarily map CONFIG_SYS_MONITOR_BASE to the 1M CONFIG_SYS_PBI_FLASH_WINDOW in AS=1. (The CONFIG_SYS_PBI_FLASH_WINDOW is the address map for the flash created by PBL/configuration word within 0 - 3.5G memory range. The u-boot image at this address has been validated by ISBC code) 2. Remove TLB entries for 0 - 3.5G created by ISBC code 3. Remove the LAW entry for the CONFIG_SYS_PBI_FLASH_WINDOW created by PBL/configuration word after switch to AS = 1 Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com> Acked-by: Wood Scott-B07421 <B07421@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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