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c6a13f3d |
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06-Mar-2024 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> |
arm64: gic: Add power up sequence for GIC-600 Arm's GIC-600 features a Power Register (GICR_PWRR), which needs to be programmed to enable redistributor operation. Power on the redistributor and wait until the power on state is reflected by checking the bit GICR_PWRR.RDPD == 0. While running U-Boot in EL3 without enabling this register, GICR_WAKER.ChildrenAsleep bit is not getting cleared and loops infinitely. This register(GICR_PWRR) must be programmed to mark the frame as powered on, before accessing other registers in the frame. Rest of initialization sequence remains the same. ARM GIC-600 IP complies with ARM GICv3 architecture. Enable this config if GIC-600 IP present. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> |
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3dd14868 |
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22-Jan-2024 |
Tom Rini <trini@konsulko.com> |
Kconfig: Centralize prompting for SYS_CONFIG_NAME Generally speaking, we do not prompt for this value and define it in the board specific Kconfig file. There are some valid use cases however today where we do prompt for this value, so instead of having this be done in a number of locations, do this at the top-level location only. This removes the question from a number of other locations and makes it consistent that when we do set the value directly, we always do it the same way. We don't need to specify the type, it's always string. Signed-off-by: Tom Rini <trini@konsulko.com> |
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724379d9 |
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10-Jan-2023 |
Ashok Reddy Soma <ashok.reddy.soma@amd.com> |
xilinx: versal-net: Add support for timer and start it Add support for starting timer by setting up time stamp generator registers. This is done only for EL3 i.e. mini U-Boot case. For other cases, it will be done TF-A. Add COUNTER_FREQUENCY and IOU_SWITCH_DIVISOR0 to Kconfig so that they can be tuned as required. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/fcd8b0dc4b45a11f5e753afff42f84738ac813da.1673336645.git.michal.simek@amd.com |
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f6aebdf6 |
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19-Sep-2022 |
Michal Simek <michal.simek@amd.com> |
arm64: versal-net: Add support for Versal NET platform Versal NET platform is based on Versal chip which is reusing a lot of IPs. For more information about new IPs please take a look at DT which describe currently supported devices. The patch is adding architecture and board support with soc detection algorithm. Generic setting should be very similar to Versal but it will likely diverge in longer run. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/320206853dc370ce290a4e7b6d0bb26b05206021.1663589964.git.michal.simek@amd.com |
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724379d9 |
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10-Jan-2023 |
Ashok Reddy Soma <ashok.reddy.soma@amd.com> |
xilinx: versal-net: Add support for timer and start it Add support for starting timer by setting up time stamp generator registers. This is done only for EL3 i.e. mini U-Boot case. For other cases, it will be done TF-A. Add COUNTER_FREQUENCY and IOU_SWITCH_DIVISOR0 to Kconfig so that they can be tuned as required. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/fcd8b0dc4b45a11f5e753afff42f84738ac813da.1673336645.git.michal.simek@amd.com |
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f6aebdf6 |
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19-Sep-2022 |
Michal Simek <michal.simek@amd.com> |
arm64: versal-net: Add support for Versal NET platform Versal NET platform is based on Versal chip which is reusing a lot of IPs. For more information about new IPs please take a look at DT which describe currently supported devices. The patch is adding architecture and board support with soc detection algorithm. Generic setting should be very similar to Versal but it will likely diverge in longer run. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/320206853dc370ce290a4e7b6d0bb26b05206021.1663589964.git.michal.simek@amd.com |
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f6aebdf6 |
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19-Sep-2022 |
Michal Simek <michal.simek@amd.com> |
arm64: versal-net: Add support for Versal NET platform Versal NET platform is based on Versal chip which is reusing a lot of IPs. For more information about new IPs please take a look at DT which describe currently supported devices. The patch is adding architecture and board support with soc detection algorithm. Generic setting should be very similar to Versal but it will likely diverge in longer run. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/320206853dc370ce290a4e7b6d0bb26b05206021.1663589964.git.michal.simek@amd.com |