#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
0e34e80f |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: mvebu: Remove <common.h> and add needed includes Remove <common.h> from all mach-mvebu files and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
225aaacf |
|
24-Mar-2022 |
Tom Rini <trini@konsulko.com> |
db-mv784mp-gp: Rename CONFIG_DB_784MP_GP to CONFIG_TARGET_DB_MV784MP_GP The value CONFIG_DB_784MP_GP is only used in the DDR code to refer to CONFIG_TARGET_DB_MV784MP_GP so just use that second value directly. Cc: Stefan Roese <sr@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefan Roese <sr@denx.de> |
#
4a86ec48 |
|
18-Nov-2021 |
Stefan Roese <sr@denx.de> |
arm: mvebu: axp/high_speed_env_lib: Switch to DM_I2C API After all Armada XP boards have been switched over from legacy I2C support to DM I2C, let's now also convert this serdes code to use the DM I2C API. Signed-off-by: Stefan Roese <sr@denx.de> |
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0a590243 |
|
08-Apr-2019 |
Stefan Roese <sr@denx.de> |
arm: mvebu: AXP: Enhance PCIe port capability configuration This patch enables the PCIe port specific link capabilities configuration for Armada XP. The weak function board_sat_r_get() was used to return a common flag for PCIe Gen1 vs Gen2 capability for all PCIe ports. This is now changed with this patch to return a bit per PCIe port (4 bits in this case, bit 0 for PCIe port 0, etc). The theadorable board uses this new feature to configure PCIe port 0 as Gen1 and all other PCIe ports as Gen2 capable. All other AXP boards using this function are not changed in the configuration and still configure all ports as PCIe Gen2. This patch also removes the parameter "pex_mode" from board_serdes_cfg_get() as this parameter was not used in any of the implementations. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a22bbfda |
|
30-Jul-2017 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
arm: mvebu: avoid possible NULL dereference It does not make sense to check if info is NULL after dereferencing it. The problem was indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Stefan Roese <sr@denx.de> |
#
d374e90b |
|
06-Apr-2017 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
arm: mvebu: Minor fixes in the AXP / A38x SERDES code - Fix spelling error of SERDES_VERSION - Remove superfluous definition of this macro - Remove unnecessary include of i2c.h Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Stefan Roese <sr@denx.de> |
#
2399e401 |
|
10-Mar-2017 |
Stefan Roese <sr@denx.de> |
arm: mvebu: AXP: Add possiblity to configure PEX detection pulse width Tests have shown that on some boards the default width of the configuration pulse for the PEX link detection might lead to non-established PCIe links (link down). Especially under certain conditions (higher temperature) and with specific PCIe devices (in the case on the theadorable board its a Atheros PCIe WLAN device). To enable a board-specific detection pulse width this weak array "serdes_pex_pulse_width[4]" is introduced which can be overwritten if needed by a board-specific version. If the board code does not provide a non-weak version of this variable, the default value will be used. So nothing is changed from the current setup on the supported board. Many thanks to Adam from Marvell for all his insights here and his suggestion about testing with a changed detection pulse width. Signed-off-by: Stefan Roese <sr@denx.de> Suggested-by: Adam Shobash <adams@marvell.com> Cc: Adam Shobash <adams@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> |
#
6202953d |
|
25-Dec-2015 |
Phil Sutter <phil@nwl.cc> |
mvebu: Add rudimental MV78230 support This adds basic support for Marvell's MV78230 SoC which belongs to the Armada XP series. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
beadff17 |
|
25-Dec-2015 |
Phil Sutter <phil@nwl.cc> |
mvebu: axp: refactor board_sat_r_get() and caller Instead of calling board_sat_r_get() only for those boards providing the satr11 value via I2C, call it for all boards and return static values for those not using I2C. In addition to that, make this a weak function to allow for board code to override it. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
e25d5a95 |
|
10-Dec-2015 |
Stefan Roese <sr@denx.de> |
arm: mvebu: Make serdes setup on Armada XP less noisy Change some of the PEX configuration output lines from always output to only ouput upon specific debug enabling. This changes the SPL output from: U-Boot SPL 2016.01-rc2-00037-g9353a7f (Dec 10 2015 - 10:27:42) High speed PHY - Version: 2.1.5 (COM-PHY-V20) Update Device ID PEX0782611ab Update Device ID PEX1782611ab Update Device ID PEX2782611ab Update Device ID PEX3782611ab Update Device ID PEX8782611ab Update PEX Device ID 0x78260 High speed PHY - Ended Successfully DDR3 Training Sequence - Ver 5.7.4 DDR3 Training Sequence - Ended Successfully to: U-Boot SPL 2016.01-rc2-00037-g9353a7f-dirty (Dec 10 2015 - 10:32:04) High speed PHY - Version: 2.1.5 (COM-PHY-V20) High speed PHY - Ended Successfully DDR3 Training Sequence - Ver 5.7.4 DDR3 Training Sequence - Ended Successfully Resulting in a little faster bootup time. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> |
#
bf0db8b8 |
|
09-Dec-2015 |
Stefan Roese <sr@denx.de> |
arm: mvebu: Add support for MV78260 This patch adds support for the dual core Armada XP variant, the MV78260. It has some minor differences to the 4-core MV78460, e.g. only 12 serdes lanes. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Phil Sutter <phil@nwl.cc> |
#
29b103c7 |
|
20-Apr-2015 |
Stefan Roese <sr@denx.de> |
arm: mvebu: serdes: Move Armada XP SERDES / PHY init code into new directory With the upcoming addition of the Armada 38x SPL support, which is not compatible to the Armada XP SERDES init code, we need to introduce a new directory infrastructure. So lets move the AXP serdes init code into a new directory. This way the A38x code can be added in a clean way. Signed-off-by: Stefan Roese <sr@denx.de> |
#
0e34e80f |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: mvebu: Remove <common.h> and add needed includes Remove <common.h> from all mach-mvebu files and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
225aaacf |
|
24-Mar-2022 |
Tom Rini <trini@konsulko.com> |
db-mv784mp-gp: Rename CONFIG_DB_784MP_GP to CONFIG_TARGET_DB_MV784MP_GP The value CONFIG_DB_784MP_GP is only used in the DDR code to refer to CONFIG_TARGET_DB_MV784MP_GP so just use that second value directly. Cc: Stefan Roese <sr@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefan Roese <sr@denx.de> |
#
4a86ec48 |
|
18-Nov-2021 |
Stefan Roese <sr@denx.de> |
arm: mvebu: axp/high_speed_env_lib: Switch to DM_I2C API After all Armada XP boards have been switched over from legacy I2C support to DM I2C, let's now also convert this serdes code to use the DM I2C API. Signed-off-by: Stefan Roese <sr@denx.de> |
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0a590243 |
|
08-Apr-2019 |
Stefan Roese <sr@denx.de> |
arm: mvebu: AXP: Enhance PCIe port capability configuration This patch enables the PCIe port specific link capabilities configuration for Armada XP. The weak function board_sat_r_get() was used to return a common flag for PCIe Gen1 vs Gen2 capability for all PCIe ports. This is now changed with this patch to return a bit per PCIe port (4 bits in this case, bit 0 for PCIe port 0, etc). The theadorable board uses this new feature to configure PCIe port 0 as Gen1 and all other PCIe ports as Gen2 capable. All other AXP boards using this function are not changed in the configuration and still configure all ports as PCIe Gen2. This patch also removes the parameter "pex_mode" from board_serdes_cfg_get() as this parameter was not used in any of the implementations. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a22bbfda |
|
30-Jul-2017 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
arm: mvebu: avoid possible NULL dereference It does not make sense to check if info is NULL after dereferencing it. The problem was indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Stefan Roese <sr@denx.de> |
#
d374e90b |
|
06-Apr-2017 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
arm: mvebu: Minor fixes in the AXP / A38x SERDES code - Fix spelling error of SERDES_VERSION - Remove superfluous definition of this macro - Remove unnecessary include of i2c.h Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Stefan Roese <sr@denx.de> |
#
2399e401 |
|
10-Mar-2017 |
Stefan Roese <sr@denx.de> |
arm: mvebu: AXP: Add possiblity to configure PEX detection pulse width Tests have shown that on some boards the default width of the configuration pulse for the PEX link detection might lead to non-established PCIe links (link down). Especially under certain conditions (higher temperature) and with specific PCIe devices (in the case on the theadorable board its a Atheros PCIe WLAN device). To enable a board-specific detection pulse width this weak array "serdes_pex_pulse_width[4]" is introduced which can be overwritten if needed by a board-specific version. If the board code does not provide a non-weak version of this variable, the default value will be used. So nothing is changed from the current setup on the supported board. Many thanks to Adam from Marvell for all his insights here and his suggestion about testing with a changed detection pulse width. Signed-off-by: Stefan Roese <sr@denx.de> Suggested-by: Adam Shobash <adams@marvell.com> Cc: Adam Shobash <adams@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> |
#
6202953d |
|
25-Dec-2015 |
Phil Sutter <phil@nwl.cc> |
mvebu: Add rudimental MV78230 support This adds basic support for Marvell's MV78230 SoC which belongs to the Armada XP series. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
beadff17 |
|
25-Dec-2015 |
Phil Sutter <phil@nwl.cc> |
mvebu: axp: refactor board_sat_r_get() and caller Instead of calling board_sat_r_get() only for those boards providing the satr11 value via I2C, call it for all boards and return static values for those not using I2C. In addition to that, make this a weak function to allow for board code to override it. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
e25d5a95 |
|
10-Dec-2015 |
Stefan Roese <sr@denx.de> |
arm: mvebu: Make serdes setup on Armada XP less noisy Change some of the PEX configuration output lines from always output to only ouput upon specific debug enabling. This changes the SPL output from: U-Boot SPL 2016.01-rc2-00037-g9353a7f (Dec 10 2015 - 10:27:42) High speed PHY - Version: 2.1.5 (COM-PHY-V20) Update Device ID PEX0782611ab Update Device ID PEX1782611ab Update Device ID PEX2782611ab Update Device ID PEX3782611ab Update Device ID PEX8782611ab Update PEX Device ID 0x78260 High speed PHY - Ended Successfully DDR3 Training Sequence - Ver 5.7.4 DDR3 Training Sequence - Ended Successfully to: U-Boot SPL 2016.01-rc2-00037-g9353a7f-dirty (Dec 10 2015 - 10:32:04) High speed PHY - Version: 2.1.5 (COM-PHY-V20) High speed PHY - Ended Successfully DDR3 Training Sequence - Ver 5.7.4 DDR3 Training Sequence - Ended Successfully Resulting in a little faster bootup time. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> |
#
bf0db8b8 |
|
09-Dec-2015 |
Stefan Roese <sr@denx.de> |
arm: mvebu: Add support for MV78260 This patch adds support for the dual core Armada XP variant, the MV78260. It has some minor differences to the 4-core MV78460, e.g. only 12 serdes lanes. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Phil Sutter <phil@nwl.cc> |
#
29b103c7 |
|
20-Apr-2015 |
Stefan Roese <sr@denx.de> |
arm: mvebu: serdes: Move Armada XP SERDES / PHY init code into new directory With the upcoming addition of the Armada 38x SPL support, which is not compatible to the Armada XP SERDES init code, we need to introduce a new directory infrastructure. So lets move the AXP serdes init code into a new directory. This way the A38x code can be added in a clean way. Signed-off-by: Stefan Roese <sr@denx.de> |
#
225aaacf |
|
24-Mar-2022 |
Tom Rini <trini@konsulko.com> |
db-mv784mp-gp: Rename CONFIG_DB_784MP_GP to CONFIG_TARGET_DB_MV784MP_GP The value CONFIG_DB_784MP_GP is only used in the DDR code to refer to CONFIG_TARGET_DB_MV784MP_GP so just use that second value directly. Cc: Stefan Roese <sr@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefan Roese <sr@denx.de> |
#
4a86ec48 |
|
18-Nov-2021 |
Stefan Roese <sr@denx.de> |
arm: mvebu: axp/high_speed_env_lib: Switch to DM_I2C API After all Armada XP boards have been switched over from legacy I2C support to DM I2C, let's now also convert this serdes code to use the DM I2C API. Signed-off-by: Stefan Roese <sr@denx.de> |
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0a590243 |
|
08-Apr-2019 |
Stefan Roese <sr@denx.de> |
arm: mvebu: AXP: Enhance PCIe port capability configuration This patch enables the PCIe port specific link capabilities configuration for Armada XP. The weak function board_sat_r_get() was used to return a common flag for PCIe Gen1 vs Gen2 capability for all PCIe ports. This is now changed with this patch to return a bit per PCIe port (4 bits in this case, bit 0 for PCIe port 0, etc). The theadorable board uses this new feature to configure PCIe port 0 as Gen1 and all other PCIe ports as Gen2 capable. All other AXP boards using this function are not changed in the configuration and still configure all ports as PCIe Gen2. This patch also removes the parameter "pex_mode" from board_serdes_cfg_get() as this parameter was not used in any of the implementations. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a22bbfda |
|
30-Jul-2017 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
arm: mvebu: avoid possible NULL dereference It does not make sense to check if info is NULL after dereferencing it. The problem was indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Stefan Roese <sr@denx.de> |
#
d374e90b |
|
06-Apr-2017 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
arm: mvebu: Minor fixes in the AXP / A38x SERDES code - Fix spelling error of SERDES_VERSION - Remove superfluous definition of this macro - Remove unnecessary include of i2c.h Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Stefan Roese <sr@denx.de> |
#
2399e401 |
|
10-Mar-2017 |
Stefan Roese <sr@denx.de> |
arm: mvebu: AXP: Add possiblity to configure PEX detection pulse width Tests have shown that on some boards the default width of the configuration pulse for the PEX link detection might lead to non-established PCIe links (link down). Especially under certain conditions (higher temperature) and with specific PCIe devices (in the case on the theadorable board its a Atheros PCIe WLAN device). To enable a board-specific detection pulse width this weak array "serdes_pex_pulse_width[4]" is introduced which can be overwritten if needed by a board-specific version. If the board code does not provide a non-weak version of this variable, the default value will be used. So nothing is changed from the current setup on the supported board. Many thanks to Adam from Marvell for all his insights here and his suggestion about testing with a changed detection pulse width. Signed-off-by: Stefan Roese <sr@denx.de> Suggested-by: Adam Shobash <adams@marvell.com> Cc: Adam Shobash <adams@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> |
#
6202953d |
|
25-Dec-2015 |
Phil Sutter <phil@nwl.cc> |
mvebu: Add rudimental MV78230 support This adds basic support for Marvell's MV78230 SoC which belongs to the Armada XP series. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
beadff17 |
|
25-Dec-2015 |
Phil Sutter <phil@nwl.cc> |
mvebu: axp: refactor board_sat_r_get() and caller Instead of calling board_sat_r_get() only for those boards providing the satr11 value via I2C, call it for all boards and return static values for those not using I2C. In addition to that, make this a weak function to allow for board code to override it. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
e25d5a95 |
|
10-Dec-2015 |
Stefan Roese <sr@denx.de> |
arm: mvebu: Make serdes setup on Armada XP less noisy Change some of the PEX configuration output lines from always output to only ouput upon specific debug enabling. This changes the SPL output from: U-Boot SPL 2016.01-rc2-00037-g9353a7f (Dec 10 2015 - 10:27:42) High speed PHY - Version: 2.1.5 (COM-PHY-V20) Update Device ID PEX0782611ab Update Device ID PEX1782611ab Update Device ID PEX2782611ab Update Device ID PEX3782611ab Update Device ID PEX8782611ab Update PEX Device ID 0x78260 High speed PHY - Ended Successfully DDR3 Training Sequence - Ver 5.7.4 DDR3 Training Sequence - Ended Successfully to: U-Boot SPL 2016.01-rc2-00037-g9353a7f-dirty (Dec 10 2015 - 10:32:04) High speed PHY - Version: 2.1.5 (COM-PHY-V20) High speed PHY - Ended Successfully DDR3 Training Sequence - Ver 5.7.4 DDR3 Training Sequence - Ended Successfully Resulting in a little faster bootup time. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> |
#
bf0db8b8 |
|
09-Dec-2015 |
Stefan Roese <sr@denx.de> |
arm: mvebu: Add support for MV78260 This patch adds support for the dual core Armada XP variant, the MV78260. It has some minor differences to the 4-core MV78460, e.g. only 12 serdes lanes. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Phil Sutter <phil@nwl.cc> |
#
29b103c7 |
|
20-Apr-2015 |
Stefan Roese <sr@denx.de> |
arm: mvebu: serdes: Move Armada XP SERDES / PHY init code into new directory With the upcoming addition of the Armada 38x SPL support, which is not compatible to the Armada XP SERDES init code, we need to introduce a new directory infrastructure. So lets move the AXP serdes init code into a new directory. This way the A38x code can be added in a clean way. Signed-off-by: Stefan Roese <sr@denx.de> |
#
4a86ec48 |
|
18-Nov-2021 |
Stefan Roese <sr@denx.de> |
arm: mvebu: axp/high_speed_env_lib: Switch to DM_I2C API After all Armada XP boards have been switched over from legacy I2C support to DM I2C, let's now also convert this serdes code to use the DM I2C API. Signed-off-by: Stefan Roese <sr@denx.de> |
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0a590243 |
|
08-Apr-2019 |
Stefan Roese <sr@denx.de> |
arm: mvebu: AXP: Enhance PCIe port capability configuration This patch enables the PCIe port specific link capabilities configuration for Armada XP. The weak function board_sat_r_get() was used to return a common flag for PCIe Gen1 vs Gen2 capability for all PCIe ports. This is now changed with this patch to return a bit per PCIe port (4 bits in this case, bit 0 for PCIe port 0, etc). The theadorable board uses this new feature to configure PCIe port 0 as Gen1 and all other PCIe ports as Gen2 capable. All other AXP boards using this function are not changed in the configuration and still configure all ports as PCIe Gen2. This patch also removes the parameter "pex_mode" from board_serdes_cfg_get() as this parameter was not used in any of the implementations. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a22bbfda |
|
30-Jul-2017 |
xypron.glpk@gmx.de <xypron.glpk@gmx.de> |
arm: mvebu: avoid possible NULL dereference It does not make sense to check if info is NULL after dereferencing it. The problem was indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Stefan Roese <sr@denx.de> |
#
d374e90b |
|
06-Apr-2017 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
arm: mvebu: Minor fixes in the AXP / A38x SERDES code - Fix spelling error of SERDES_VERSION - Remove superfluous definition of this macro - Remove unnecessary include of i2c.h Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Stefan Roese <sr@denx.de> |
#
2399e401 |
|
10-Mar-2017 |
Stefan Roese <sr@denx.de> |
arm: mvebu: AXP: Add possiblity to configure PEX detection pulse width Tests have shown that on some boards the default width of the configuration pulse for the PEX link detection might lead to non-established PCIe links (link down). Especially under certain conditions (higher temperature) and with specific PCIe devices (in the case on the theadorable board its a Atheros PCIe WLAN device). To enable a board-specific detection pulse width this weak array "serdes_pex_pulse_width[4]" is introduced which can be overwritten if needed by a board-specific version. If the board code does not provide a non-weak version of this variable, the default value will be used. So nothing is changed from the current setup on the supported board. Many thanks to Adam from Marvell for all his insights here and his suggestion about testing with a changed detection pulse width. Signed-off-by: Stefan Roese <sr@denx.de> Suggested-by: Adam Shobash <adams@marvell.com> Cc: Adam Shobash <adams@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> |
#
6202953d |
|
25-Dec-2015 |
Phil Sutter <phil@nwl.cc> |
mvebu: Add rudimental MV78230 support This adds basic support for Marvell's MV78230 SoC which belongs to the Armada XP series. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
beadff17 |
|
25-Dec-2015 |
Phil Sutter <phil@nwl.cc> |
mvebu: axp: refactor board_sat_r_get() and caller Instead of calling board_sat_r_get() only for those boards providing the satr11 value via I2C, call it for all boards and return static values for those not using I2C. In addition to that, make this a weak function to allow for board code to override it. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
e25d5a95 |
|
10-Dec-2015 |
Stefan Roese <sr@denx.de> |
arm: mvebu: Make serdes setup on Armada XP less noisy Change some of the PEX configuration output lines from always output to only ouput upon specific debug enabling. This changes the SPL output from: U-Boot SPL 2016.01-rc2-00037-g9353a7f (Dec 10 2015 - 10:27:42) High speed PHY - Version: 2.1.5 (COM-PHY-V20) Update Device ID PEX0782611ab Update Device ID PEX1782611ab Update Device ID PEX2782611ab Update Device ID PEX3782611ab Update Device ID PEX8782611ab Update PEX Device ID 0x78260 High speed PHY - Ended Successfully DDR3 Training Sequence - Ver 5.7.4 DDR3 Training Sequence - Ended Successfully to: U-Boot SPL 2016.01-rc2-00037-g9353a7f-dirty (Dec 10 2015 - 10:32:04) High speed PHY - Version: 2.1.5 (COM-PHY-V20) High speed PHY - Ended Successfully DDR3 Training Sequence - Ver 5.7.4 DDR3 Training Sequence - Ended Successfully Resulting in a little faster bootup time. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> |
#
bf0db8b8 |
|
09-Dec-2015 |
Stefan Roese <sr@denx.de> |
arm: mvebu: Add support for MV78260 This patch adds support for the dual core Armada XP variant, the MV78260. It has some minor differences to the 4-core MV78460, e.g. only 12 serdes lanes. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Phil Sutter <phil@nwl.cc> |
#
29b103c7 |
|
20-Apr-2015 |
Stefan Roese <sr@denx.de> |
arm: mvebu: serdes: Move Armada XP SERDES / PHY init code into new directory With the upcoming addition of the Armada 38x SPL support, which is not compatible to the Armada XP SERDES init code, we need to introduce a new directory infrastructure. So lets move the AXP serdes init code into a new directory. This way the A38x code can be added in a clean way. Signed-off-by: Stefan Roese <sr@denx.de> |
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0a590243 |
|
08-Apr-2019 |
Stefan Roese <sr@denx.de> |
arm: mvebu: AXP: Enhance PCIe port capability configuration This patch enables the PCIe port specific link capabilities configuration for Armada XP. The weak function board_sat_r_get() was used to return a common flag for PCIe Gen1 vs Gen2 capability for all PCIe ports. This is now changed with this patch to return a bit per PCIe port (4 bits in this case, bit 0 for PCIe port 0, etc). The theadorable board uses this new feature to configure PCIe port 0 as Gen1 and all other PCIe ports as Gen2 capable. All other AXP boards using this function are not changed in the configuration and still configure all ports as PCIe Gen2. This patch also removes the parameter "pex_mode" from board_serdes_cfg_get() as this parameter was not used in any of the implementations. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a22bbfda |
|
30-Jul-2017 |
xypron.glpk@gmx.de <xypron.glpk@gmx.de> |
arm: mvebu: avoid possible NULL dereference It does not make sense to check if info is NULL after dereferencing it. The problem was indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Stefan Roese <sr@denx.de> |
#
d374e90b |
|
06-Apr-2017 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
arm: mvebu: Minor fixes in the AXP / A38x SERDES code - Fix spelling error of SERDES_VERSION - Remove superfluous definition of this macro - Remove unnecessary include of i2c.h Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Stefan Roese <sr@denx.de> |
#
2399e401 |
|
10-Mar-2017 |
Stefan Roese <sr@denx.de> |
arm: mvebu: AXP: Add possiblity to configure PEX detection pulse width Tests have shown that on some boards the default width of the configuration pulse for the PEX link detection might lead to non-established PCIe links (link down). Especially under certain conditions (higher temperature) and with specific PCIe devices (in the case on the theadorable board its a Atheros PCIe WLAN device). To enable a board-specific detection pulse width this weak array "serdes_pex_pulse_width[4]" is introduced which can be overwritten if needed by a board-specific version. If the board code does not provide a non-weak version of this variable, the default value will be used. So nothing is changed from the current setup on the supported board. Many thanks to Adam from Marvell for all his insights here and his suggestion about testing with a changed detection pulse width. Signed-off-by: Stefan Roese <sr@denx.de> Suggested-by: Adam Shobash <adams@marvell.com> Cc: Adam Shobash <adams@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> |
#
6202953d |
|
25-Dec-2015 |
Phil Sutter <phil@nwl.cc> |
mvebu: Add rudimental MV78230 support This adds basic support for Marvell's MV78230 SoC which belongs to the Armada XP series. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
beadff17 |
|
25-Dec-2015 |
Phil Sutter <phil@nwl.cc> |
mvebu: axp: refactor board_sat_r_get() and caller Instead of calling board_sat_r_get() only for those boards providing the satr11 value via I2C, call it for all boards and return static values for those not using I2C. In addition to that, make this a weak function to allow for board code to override it. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
e25d5a95 |
|
10-Dec-2015 |
Stefan Roese <sr@denx.de> |
arm: mvebu: Make serdes setup on Armada XP less noisy Change some of the PEX configuration output lines from always output to only ouput upon specific debug enabling. This changes the SPL output from: U-Boot SPL 2016.01-rc2-00037-g9353a7f (Dec 10 2015 - 10:27:42) High speed PHY - Version: 2.1.5 (COM-PHY-V20) Update Device ID PEX0782611ab Update Device ID PEX1782611ab Update Device ID PEX2782611ab Update Device ID PEX3782611ab Update Device ID PEX8782611ab Update PEX Device ID 0x78260 High speed PHY - Ended Successfully DDR3 Training Sequence - Ver 5.7.4 DDR3 Training Sequence - Ended Successfully to: U-Boot SPL 2016.01-rc2-00037-g9353a7f-dirty (Dec 10 2015 - 10:32:04) High speed PHY - Version: 2.1.5 (COM-PHY-V20) High speed PHY - Ended Successfully DDR3 Training Sequence - Ver 5.7.4 DDR3 Training Sequence - Ended Successfully Resulting in a little faster bootup time. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> |
#
bf0db8b8 |
|
09-Dec-2015 |
Stefan Roese <sr@denx.de> |
arm: mvebu: Add support for MV78260 This patch adds support for the dual core Armada XP variant, the MV78260. It has some minor differences to the 4-core MV78460, e.g. only 12 serdes lanes. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Phil Sutter <phil@nwl.cc> |
#
29b103c7 |
|
20-Apr-2015 |
Stefan Roese <sr@denx.de> |
arm: mvebu: serdes: Move Armada XP SERDES / PHY init code into new directory With the upcoming addition of the Armada 38x SPL support, which is not compatible to the Armada XP SERDES init code, we need to introduce a new directory infrastructure. So lets move the AXP serdes init code into a new directory. This way the A38x code can be added in a clean way. Signed-off-by: Stefan Roese <sr@denx.de> |
#
0a590243 |
|
08-Apr-2019 |
Stefan Roese <sr@denx.de> |
arm: mvebu: AXP: Enhance PCIe port capability configuration This patch enables the PCIe port specific link capabilities configuration for Armada XP. The weak function board_sat_r_get() was used to return a common flag for PCIe Gen1 vs Gen2 capability for all PCIe ports. This is now changed with this patch to return a bit per PCIe port (4 bits in this case, bit 0 for PCIe port 0, etc). The theadorable board uses this new feature to configure PCIe port 0 as Gen1 and all other PCIe ports as Gen2 capable. All other AXP boards using this function are not changed in the configuration and still configure all ports as PCIe Gen2. This patch also removes the parameter "pex_mode" from board_serdes_cfg_get() as this parameter was not used in any of the implementations. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a22bbfda |
|
30-Jul-2017 |
xypron.glpk@gmx.de <xypron.glpk@gmx.de> |
arm: mvebu: avoid possible NULL dereference It does not make sense to check if info is NULL after dereferencing it. The problem was indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Stefan Roese <sr@denx.de> |
#
d374e90b |
|
06-Apr-2017 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
arm: mvebu: Minor fixes in the AXP / A38x SERDES code - Fix spelling error of SERDES_VERSION - Remove superfluous definition of this macro - Remove unnecessary include of i2c.h Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Stefan Roese <sr@denx.de> |
#
2399e401 |
|
10-Mar-2017 |
Stefan Roese <sr@denx.de> |
arm: mvebu: AXP: Add possiblity to configure PEX detection pulse width Tests have shown that on some boards the default width of the configuration pulse for the PEX link detection might lead to non-established PCIe links (link down). Especially under certain conditions (higher temperature) and with specific PCIe devices (in the case on the theadorable board its a Atheros PCIe WLAN device). To enable a board-specific detection pulse width this weak array "serdes_pex_pulse_width[4]" is introduced which can be overwritten if needed by a board-specific version. If the board code does not provide a non-weak version of this variable, the default value will be used. So nothing is changed from the current setup on the supported board. Many thanks to Adam from Marvell for all his insights here and his suggestion about testing with a changed detection pulse width. Signed-off-by: Stefan Roese <sr@denx.de> Suggested-by: Adam Shobash <adams@marvell.com> Cc: Adam Shobash <adams@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> |
#
6202953d |
|
25-Dec-2015 |
Phil Sutter <phil@nwl.cc> |
mvebu: Add rudimental MV78230 support This adds basic support for Marvell's MV78230 SoC which belongs to the Armada XP series. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
beadff17 |
|
25-Dec-2015 |
Phil Sutter <phil@nwl.cc> |
mvebu: axp: refactor board_sat_r_get() and caller Instead of calling board_sat_r_get() only for those boards providing the satr11 value via I2C, call it for all boards and return static values for those not using I2C. In addition to that, make this a weak function to allow for board code to override it. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
e25d5a95 |
|
10-Dec-2015 |
Stefan Roese <sr@denx.de> |
arm: mvebu: Make serdes setup on Armada XP less noisy Change some of the PEX configuration output lines from always output to only ouput upon specific debug enabling. This changes the SPL output from: U-Boot SPL 2016.01-rc2-00037-g9353a7f (Dec 10 2015 - 10:27:42) High speed PHY - Version: 2.1.5 (COM-PHY-V20) Update Device ID PEX0782611ab Update Device ID PEX1782611ab Update Device ID PEX2782611ab Update Device ID PEX3782611ab Update Device ID PEX8782611ab Update PEX Device ID 0x78260 High speed PHY - Ended Successfully DDR3 Training Sequence - Ver 5.7.4 DDR3 Training Sequence - Ended Successfully to: U-Boot SPL 2016.01-rc2-00037-g9353a7f-dirty (Dec 10 2015 - 10:32:04) High speed PHY - Version: 2.1.5 (COM-PHY-V20) High speed PHY - Ended Successfully DDR3 Training Sequence - Ver 5.7.4 DDR3 Training Sequence - Ended Successfully Resulting in a little faster bootup time. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> |
#
bf0db8b8 |
|
09-Dec-2015 |
Stefan Roese <sr@denx.de> |
arm: mvebu: Add support for MV78260 This patch adds support for the dual core Armada XP variant, the MV78260. It has some minor differences to the 4-core MV78460, e.g. only 12 serdes lanes. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Phil Sutter <phil@nwl.cc> |
#
29b103c7 |
|
20-Apr-2015 |
Stefan Roese <sr@denx.de> |
arm: mvebu: serdes: Move Armada XP SERDES / PHY init code into new directory With the upcoming addition of the Armada 38x SPL support, which is not compatible to the Armada XP SERDES init code, we need to introduce a new directory infrastructure. So lets move the AXP serdes init code into a new directory. This way the A38x code can be added in a clean way. Signed-off-by: Stefan Roese <sr@denx.de> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
a22bbfda |
|
30-Jul-2017 |
xypron.glpk@gmx.de <xypron.glpk@gmx.de> |
arm: mvebu: avoid possible NULL dereference It does not make sense to check if info is NULL after dereferencing it. The problem was indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
d374e90b |
|
06-Apr-2017 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
arm: mvebu: Minor fixes in the AXP / A38x SERDES code - Fix spelling error of SERDES_VERSION - Remove superfluous definition of this macro - Remove unnecessary include of i2c.h Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
6bbe0924 |
|
10-Mar-2017 |
Stefan Roese <sr@denx.de> |
arm: mvebu: AXP: Add possiblity to configure PEX detection pulse width Tests have shown that on some boards the default width of the configuration pulse for the PEX link detection might lead to non-established PCIe links (link down). Especially under certain conditions (higher temperature) and with specific PCIe devices (in the case on the theadorable board its a Atheros PCIe WLAN device). To enable a board-specific detection pulse width this weak array "serdes_pex_pulse_width[4]" is introduced which can be overwritten if needed by a board-specific version. If the board code does not provide a non-weak version of this variable, the default value will be used. So nothing is changed from the current setup on the supported board. Many thanks to Adam from Marvell for all his insights here and his suggestion about testing with a changed detection pulse width. Signed-off-by: Stefan Roese <sr@denx.de> Suggested-by: Adam Shobash <adams@marvell.com> Cc: Adam Shobash <adams@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
2399e401 |
|
10-Mar-2017 |
Stefan Roese <sr@denx.de> |
arm: mvebu: AXP: Add possiblity to configure PEX detection pulse width Tests have shown that on some boards the default width of the configuration pulse for the PEX link detection might lead to non-established PCIe links (link down). Especially under certain conditions (higher temperature) and with specific PCIe devices (in the case on the theadorable board its a Atheros PCIe WLAN device). To enable a board-specific detection pulse width this weak array "serdes_pex_pulse_width[4]" is introduced which can be overwritten if needed by a board-specific version. If the board code does not provide a non-weak version of this variable, the default value will be used. So nothing is changed from the current setup on the supported board. Many thanks to Adam from Marvell for all his insights here and his suggestion about testing with a changed detection pulse width. Signed-off-by: Stefan Roese <sr@denx.de> Suggested-by: Adam Shobash <adams@marvell.com> Cc: Adam Shobash <adams@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
6202953d |
|
25-Dec-2015 |
Phil Sutter <phil@nwl.cc> |
mvebu: Add rudimental MV78230 support This adds basic support for Marvell's MV78230 SoC which belongs to the Armada XP series. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
beadff17 |
|
25-Dec-2015 |
Phil Sutter <phil@nwl.cc> |
mvebu: axp: refactor board_sat_r_get() and caller Instead of calling board_sat_r_get() only for those boards providing the satr11 value via I2C, call it for all boards and return static values for those not using I2C. In addition to that, make this a weak function to allow for board code to override it. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
e25d5a95 |
|
10-Dec-2015 |
Stefan Roese <sr@denx.de> |
arm: mvebu: Make serdes setup on Armada XP less noisy Change some of the PEX configuration output lines from always output to only ouput upon specific debug enabling. This changes the SPL output from: U-Boot SPL 2016.01-rc2-00037-g9353a7f (Dec 10 2015 - 10:27:42) High speed PHY - Version: 2.1.5 (COM-PHY-V20) Update Device ID PEX0782611ab Update Device ID PEX1782611ab Update Device ID PEX2782611ab Update Device ID PEX3782611ab Update Device ID PEX8782611ab Update PEX Device ID 0x78260 High speed PHY - Ended Successfully DDR3 Training Sequence - Ver 5.7.4 DDR3 Training Sequence - Ended Successfully to: U-Boot SPL 2016.01-rc2-00037-g9353a7f-dirty (Dec 10 2015 - 10:32:04) High speed PHY - Version: 2.1.5 (COM-PHY-V20) High speed PHY - Ended Successfully DDR3 Training Sequence - Ver 5.7.4 DDR3 Training Sequence - Ended Successfully Resulting in a little faster bootup time. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
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bf0db8b8 |
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09-Dec-2015 |
Stefan Roese <sr@denx.de> |
arm: mvebu: Add support for MV78260 This patch adds support for the dual core Armada XP variant, the MV78260. It has some minor differences to the 4-core MV78460, e.g. only 12 serdes lanes. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Phil Sutter <phil@nwl.cc>
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29b103c7 |
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20-Apr-2015 |
Stefan Roese <sr@denx.de> |
arm: mvebu: serdes: Move Armada XP SERDES / PHY init code into new directory With the upcoming addition of the Armada 38x SPL support, which is not compatible to the Armada XP SERDES init code, we need to introduce a new directory infrastructure. So lets move the AXP serdes init code into a new directory. This way the A38x code can be added in a clean way. Signed-off-by: Stefan Roese <sr@denx.de>
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