#
6490c127 |
|
27-Apr-2023 |
Peng Fan <peng.fan@nxp.com> |
imx8ulp: build ahab The ahab was missed to be compiled, so add it back. Signed-off-by: Peng Fan <peng.fan@nxp.com> |
#
74a39c15 |
|
31-Jan-2023 |
Ye Li <ye.li@nxp.com> |
imx8ulp_evk: Change to use DDR driver Remove the DDR initialization codes from board and enable the iMX8ULP DDR driver. Signed-off-by: Ye Li <ye.li@nxp.com> |
#
a092f333 |
|
06-Apr-2022 |
Peng Fan <peng.fan@nxp.com> |
imx: imx8ulp: add ND/LD clock Add a new ddr script, defconfig for ND Configure the clock for ND mode changing A35 to 960MHz for OD mode Update NIC CLK for the various modes Introduce clock_init_early/late, late is used after pmic voltage setting, early is used in the very early stage for upower mu, lpuart and etc. Note: NIC runs at 324MHz, 442MHz has some random kernel hang issue with cpuidle enabled now. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> |
#
0f709635 |
|
18-Mar-2022 |
Ye Li <ye.li@nxp.com> |
imx8ulp: Disable SPL exception vector Disable SPL exception vector which causes issue to ROM patch execution when SPL calling ROM API. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> |
#
3f2b4d72 |
|
07-Aug-2021 |
Peng Fan <peng.fan@nxp.com> |
arm: imx: add i.MX8ULP EVK support Add i.MX8ULP EVK basic support, support SD/I2C/ENET/LPUART Log as below: I would keep some debug info for now, and after we move to be stable and production launch, we could drop that. U-Boot SPL 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800) Normal Boot upower_init: soc_id=48 upower_init: version:11.11.6 upower_init: start uPower RAM service user_upwr_rdy_callb: soc=b user_upwr_rdy_callb: RAM version:12.6 Turn on switches ok Turn on memories ok Clear DDR retention ok Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F0 frequency. Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F2 frequency. Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F2 frequency. complete De-Skew PLL is locked and ready WDT: Not found! Trying to boot from BOOTROM image offset 0x8000, pagesize 0x200, ivt offset 0x0 Load image from 0x3a800 by ROM_API NOTICE: BL31: v2.4(release):imx_5.10.35_2.0.0_imx8ulp_er-10-gf37e59b94 NOTICE: BL31: Built : 01:56:58, Jun 29 2021 NOTICE: upower_init: start uPower RAM service NOTICE: user_upwr_rdy_callb: soc=b NOTICE: user_upwr_rdy_callb: RAM version:12.6 U-Boot 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800) CPU: Freescale i.MX8ULP rev1.0 at 744 MHz Reset cause: POR Boot mode: Single boot Model: FSL i.MX8ULP EVK DRAM: 2 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 2 Loading Environment from MMC... *** Warning - bad CRC, using default environment In: serial@293a0000 Out: serial@293a0000 Err: serial@293a0000 Net: Warning: ethernet@29950000 (eth0) using random MAC address - 96:35:88:62:e0:44 eth0: ethernet@29950000 Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <peng.fan@nxp.com> |
#
19b990b4 |
|
07-Aug-2021 |
Peng Fan <peng.fan@nxp.com> |
arm: imx: add i.MX8ULP basic Kconfig option Add i.MX8ULP related basic Kconfig option, which will be used later. Signed-off-by: Peng Fan <peng.fan@nxp.com> |
#
74a39c15 |
|
31-Jan-2023 |
Ye Li <ye.li@nxp.com> |
imx8ulp_evk: Change to use DDR driver Remove the DDR initialization codes from board and enable the iMX8ULP DDR driver. Signed-off-by: Ye Li <ye.li@nxp.com> |
#
a092f333 |
|
06-Apr-2022 |
Peng Fan <peng.fan@nxp.com> |
imx: imx8ulp: add ND/LD clock Add a new ddr script, defconfig for ND Configure the clock for ND mode changing A35 to 960MHz for OD mode Update NIC CLK for the various modes Introduce clock_init_early/late, late is used after pmic voltage setting, early is used in the very early stage for upower mu, lpuart and etc. Note: NIC runs at 324MHz, 442MHz has some random kernel hang issue with cpuidle enabled now. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> |
#
0f709635 |
|
18-Mar-2022 |
Ye Li <ye.li@nxp.com> |
imx8ulp: Disable SPL exception vector Disable SPL exception vector which causes issue to ROM patch execution when SPL calling ROM API. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> |
#
3f2b4d72 |
|
07-Aug-2021 |
Peng Fan <peng.fan@nxp.com> |
arm: imx: add i.MX8ULP EVK support Add i.MX8ULP EVK basic support, support SD/I2C/ENET/LPUART Log as below: I would keep some debug info for now, and after we move to be stable and production launch, we could drop that. U-Boot SPL 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800) Normal Boot upower_init: soc_id=48 upower_init: version:11.11.6 upower_init: start uPower RAM service user_upwr_rdy_callb: soc=b user_upwr_rdy_callb: RAM version:12.6 Turn on switches ok Turn on memories ok Clear DDR retention ok Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F0 frequency. Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F2 frequency. Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F2 frequency. complete De-Skew PLL is locked and ready WDT: Not found! Trying to boot from BOOTROM image offset 0x8000, pagesize 0x200, ivt offset 0x0 Load image from 0x3a800 by ROM_API NOTICE: BL31: v2.4(release):imx_5.10.35_2.0.0_imx8ulp_er-10-gf37e59b94 NOTICE: BL31: Built : 01:56:58, Jun 29 2021 NOTICE: upower_init: start uPower RAM service NOTICE: user_upwr_rdy_callb: soc=b NOTICE: user_upwr_rdy_callb: RAM version:12.6 U-Boot 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800) CPU: Freescale i.MX8ULP rev1.0 at 744 MHz Reset cause: POR Boot mode: Single boot Model: FSL i.MX8ULP EVK DRAM: 2 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 2 Loading Environment from MMC... *** Warning - bad CRC, using default environment In: serial@293a0000 Out: serial@293a0000 Err: serial@293a0000 Net: Warning: ethernet@29950000 (eth0) using random MAC address - 96:35:88:62:e0:44 eth0: ethernet@29950000 Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <peng.fan@nxp.com> |
#
19b990b4 |
|
07-Aug-2021 |
Peng Fan <peng.fan@nxp.com> |
arm: imx: add i.MX8ULP basic Kconfig option Add i.MX8ULP related basic Kconfig option, which will be used later. Signed-off-by: Peng Fan <peng.fan@nxp.com> |
#
a092f333 |
|
06-Apr-2022 |
Peng Fan <peng.fan@nxp.com> |
imx: imx8ulp: add ND/LD clock Add a new ddr script, defconfig for ND Configure the clock for ND mode changing A35 to 960MHz for OD mode Update NIC CLK for the various modes Introduce clock_init_early/late, late is used after pmic voltage setting, early is used in the very early stage for upower mu, lpuart and etc. Note: NIC runs at 324MHz, 442MHz has some random kernel hang issue with cpuidle enabled now. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> |
#
0f709635 |
|
18-Mar-2022 |
Ye Li <ye.li@nxp.com> |
imx8ulp: Disable SPL exception vector Disable SPL exception vector which causes issue to ROM patch execution when SPL calling ROM API. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> |
#
3f2b4d72 |
|
07-Aug-2021 |
Peng Fan <peng.fan@nxp.com> |
arm: imx: add i.MX8ULP EVK support Add i.MX8ULP EVK basic support, support SD/I2C/ENET/LPUART Log as below: I would keep some debug info for now, and after we move to be stable and production launch, we could drop that. U-Boot SPL 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800) Normal Boot upower_init: soc_id=48 upower_init: version:11.11.6 upower_init: start uPower RAM service user_upwr_rdy_callb: soc=b user_upwr_rdy_callb: RAM version:12.6 Turn on switches ok Turn on memories ok Clear DDR retention ok Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F0 frequency. Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F2 frequency. Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F2 frequency. complete De-Skew PLL is locked and ready WDT: Not found! Trying to boot from BOOTROM image offset 0x8000, pagesize 0x200, ivt offset 0x0 Load image from 0x3a800 by ROM_API NOTICE: BL31: v2.4(release):imx_5.10.35_2.0.0_imx8ulp_er-10-gf37e59b94 NOTICE: BL31: Built : 01:56:58, Jun 29 2021 NOTICE: upower_init: start uPower RAM service NOTICE: user_upwr_rdy_callb: soc=b NOTICE: user_upwr_rdy_callb: RAM version:12.6 U-Boot 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800) CPU: Freescale i.MX8ULP rev1.0 at 744 MHz Reset cause: POR Boot mode: Single boot Model: FSL i.MX8ULP EVK DRAM: 2 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 2 Loading Environment from MMC... *** Warning - bad CRC, using default environment In: serial@293a0000 Out: serial@293a0000 Err: serial@293a0000 Net: Warning: ethernet@29950000 (eth0) using random MAC address - 96:35:88:62:e0:44 eth0: ethernet@29950000 Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <peng.fan@nxp.com> |
#
19b990b4 |
|
07-Aug-2021 |
Peng Fan <peng.fan@nxp.com> |
arm: imx: add i.MX8ULP basic Kconfig option Add i.MX8ULP related basic Kconfig option, which will be used later. Signed-off-by: Peng Fan <peng.fan@nxp.com> |
#
3f2b4d72 |
|
07-Aug-2021 |
Peng Fan <peng.fan@nxp.com> |
arm: imx: add i.MX8ULP EVK support Add i.MX8ULP EVK basic support, support SD/I2C/ENET/LPUART Log as below: I would keep some debug info for now, and after we move to be stable and production launch, we could drop that. U-Boot SPL 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800) Normal Boot upower_init: soc_id=48 upower_init: version:11.11.6 upower_init: start uPower RAM service user_upwr_rdy_callb: soc=b user_upwr_rdy_callb: RAM version:12.6 Turn on switches ok Turn on memories ok Clear DDR retention ok Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F0 frequency. Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F2 frequency. Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F2 frequency. complete De-Skew PLL is locked and ready WDT: Not found! Trying to boot from BOOTROM image offset 0x8000, pagesize 0x200, ivt offset 0x0 Load image from 0x3a800 by ROM_API NOTICE: BL31: v2.4(release):imx_5.10.35_2.0.0_imx8ulp_er-10-gf37e59b94 NOTICE: BL31: Built : 01:56:58, Jun 29 2021 NOTICE: upower_init: start uPower RAM service NOTICE: user_upwr_rdy_callb: soc=b NOTICE: user_upwr_rdy_callb: RAM version:12.6 U-Boot 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800) CPU: Freescale i.MX8ULP rev1.0 at 744 MHz Reset cause: POR Boot mode: Single boot Model: FSL i.MX8ULP EVK DRAM: 2 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 2 Loading Environment from MMC... *** Warning - bad CRC, using default environment In: serial@293a0000 Out: serial@293a0000 Err: serial@293a0000 Net: Warning: ethernet@29950000 (eth0) using random MAC address - 96:35:88:62:e0:44 eth0: ethernet@29950000 Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <peng.fan@nxp.com> |
#
19b990b4 |
|
07-Aug-2021 |
Peng Fan <peng.fan@nxp.com> |
arm: imx: add i.MX8ULP basic Kconfig option Add i.MX8ULP related basic Kconfig option, which will be used later. Signed-off-by: Peng Fan <peng.fan@nxp.com> |