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4ab38f68 |
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06-Apr-2022 |
Ye Li <ye.li@nxp.com> |
imx: imx8ulp_evk: Skip init DDR for reboot in dual boot mode When M33 is LPAV owner in dual boot, DDR, PCC5, CGC2 won't be reset during APD reset. So no need to init DDR again after reboot, but need to reconfigure the PLL4 PFD/PFDDIV/LPAV NIC etc, because kernel may change or disable some of them. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> |
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a092f333 |
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06-Apr-2022 |
Peng Fan <peng.fan@nxp.com> |
imx: imx8ulp: add ND/LD clock Add a new ddr script, defconfig for ND Configure the clock for ND mode changing A35 to 960MHz for OD mode Update NIC CLK for the various modes Introduce clock_init_early/late, late is used after pmic voltage setting, early is used in the very early stage for upower mu, lpuart and etc. Note: NIC runs at 324MHz, 442MHz has some random kernel hang issue with cpuidle enabled now. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> |
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dc77d0f9 |
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28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: clock: Handle the DDRLOCKED when setting DDR clock The DDRLOCKED bit in CGC2 DDRCLK will auto lock up and down by HW according to DDR DIV updating or DDR CLK halt status change. So DDR PCC disable/enable will trigger the lock up/down flow. We need wait until unlock to ensure clock is ready. And before configuring the DDRCLK DIV, we need polling the DDRLOCKED until it is unlocked. Otherwise writing ti DIV bits will not set. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> |
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0f9b10aa |
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28-Oct-2021 |
Alice Guo <alice.guo@nxp.com> |
imx8ulp: clock: Support to enable/disable the ADC1 clock This patch implements enable_adc1_clk() to enable or disable the ADC1 clock on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Alice Guo <alice.guo@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> |
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5ff18da3 |
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28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: clock: Support LPAV clocks in cgc and pcc Add the PCC5 clocks support and more LPAV clocks and PLL4 PFD in CGC. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> |
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a84dab4f |
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07-Aug-2021 |
Peng Fan <peng.fan@nxp.com> |
arm: imx8ulp: add clock support Add i.MX8ULP clock support Signed-off-by: Peng Fan <peng.fan@nxp.com> |
#
dc77d0f9 |
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28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: clock: Handle the DDRLOCKED when setting DDR clock The DDRLOCKED bit in CGC2 DDRCLK will auto lock up and down by HW according to DDR DIV updating or DDR CLK halt status change. So DDR PCC disable/enable will trigger the lock up/down flow. We need wait until unlock to ensure clock is ready. And before configuring the DDRCLK DIV, we need polling the DDRLOCKED until it is unlocked. Otherwise writing ti DIV bits will not set. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> |
#
0f9b10aa |
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28-Oct-2021 |
Alice Guo <alice.guo@nxp.com> |
imx8ulp: clock: Support to enable/disable the ADC1 clock This patch implements enable_adc1_clk() to enable or disable the ADC1 clock on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Alice Guo <alice.guo@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> |
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5ff18da3 |
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28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: clock: Support LPAV clocks in cgc and pcc Add the PCC5 clocks support and more LPAV clocks and PLL4 PFD in CGC. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> |
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a84dab4f |
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07-Aug-2021 |
Peng Fan <peng.fan@nxp.com> |
arm: imx8ulp: add clock support Add i.MX8ULP clock support Signed-off-by: Peng Fan <peng.fan@nxp.com> |
#
a84dab4f |
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07-Aug-2021 |
Peng Fan <peng.fan@nxp.com> |
arm: imx8ulp: add clock support Add i.MX8ULP clock support Signed-off-by: Peng Fan <peng.fan@nxp.com> |