#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
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#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
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#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
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#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
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#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
81f3a665 |
|
16-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
common: Convert *.c/h from UTF-8 to ASCII enconfing Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3b06577a |
|
29-Mar-2022 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
09140113 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
command: Remove the cmd_tbl_t typedef We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
0d9d557d |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6252faa0 |
|
26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
8c487539 |
|
28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
6252faa0 |
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26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
8c487539 |
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28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
4909b89e |
|
29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
6252faa0 |
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26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
8c487539 |
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28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
6252faa0 |
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26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
8c487539 |
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28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
6252faa0 |
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26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
8c487539 |
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28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
6252faa0 |
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26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
8c487539 |
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28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
6252faa0 |
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26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
8c487539 |
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28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
6252faa0 |
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26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
8c487539 |
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28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
6252faa0 |
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26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
8c487539 |
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28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
6252faa0 |
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26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
8c487539 |
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28-Nov-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8, lx2160a: Initialize ethernet array in serdes_init Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
4909b89e |
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29-Oct-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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6252faa0 |
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26-Sep-2018 |
Priyanka Jain <priyanka.jain@nxp.com> |
armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
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a1f95ff7 |
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17-Jan-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: lsch3: Add serdes and DDR voltage setup Adds SERDES voltage and reset SERDES lanes API and makes enable/disable DDR controller support 0.9V API common. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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6d9b82d0 |
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31-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
armv8: ls1088a: Add NXP LS1088A SoC support LS1088A is compliant with the Layerscape Chassis Generation 3 with eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4 SDRAM memory controller with ECC, Data path acceleration architecture 2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs), QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> [YS: Revised commit message] Reviewed-by: York Sun <york.sun@nxp.com>
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1f55a938 |
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05-May-2017 |
Santan Kumar <santan.kumar@nxp.com> |
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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7b45b383 |
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15-Feb-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8:fsl-layerscape: Avoid RCWSR28 register hard-coding SerDes information is not necessary to be present in RCWSR29 register. It may vary from SoC to SoC. So Avoid RCWSR28 register hard-coding. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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1b7dba99 |
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15-Feb-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
arm: fsl-layerscape: Move QSGMII wriop_init to SoC file MAC number used per QSGMII is not fixed. It may wary from SoC to SoC. So move QSGMII wriop_init_dpmac() to SoC file. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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1221ce45 |
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20-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace #include <asm/errno.h> with <linux/errno.h> Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com>
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71fe2225 |
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02-Aug-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
fsl: serdes: ensure accessing the initialized maps of serdes protocol Up to now, the function is_serdes_configed() doesn't check if the map of serdes protocol is initialized before accessing it. The function is_serdes_configed() will get wrong result when it was called before the serdes protocol maps initialized. As the first element of the map isn't used for any device, so use it as the flag to indicate if the map has been initialized. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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1a338921 |
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28-Nov-2015 |
Tom Rini <trini@konsulko.com> |
fsl_*_serdes.c: Modify memset call in serdes_init GCC 5.x does not like sizeof(array_variable) and errors out. Change these calls to be instead sizeof(u8) (as that's what serdes_prtcl_map is) * SERDES_PRCTL_COUNT (the number of array elements). Cc: York Sun <yorksun@freescale.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com>
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99e904c1 |
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03-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: lsch3: Fix lane protocol parsing logic Current implementation only consider SGMIIs for dpmac initialization. XFI serdes protocols also uses dpmac. Also, fix lane protocol parsing logic to consider both XFIs and SGMIIs. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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9f3183d2 |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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