armv7: fsl: remove sata support

Remove the old implementation in order to enable DM for sata

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

nxp: ls102xa: add LS1 PSCI system suspend

The deep sleep function of LS1 platform, is mapped into PSCI system
suspend function, this patch adds implementation of it.

Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

arm: ls1021a: merge SoC specific code in a separate file

Create a soc.c file to put the code for soc special settings.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

arm: ls1021a: Add sata support on qds and twr board

Freescale ARM-based Layerscape LS102xA contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls1021aqds and ls1021atwr boards.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

arm/ls102xa: Add PSCI support for ls102xa

Base on PSCI services, implement CPU_ON/CPU_OFF for ls102xa platform.

Tested on LS1021AQDS, LS1021ATWR.
Test CPU hotplug times: 60K
Test kernel boot times: 1.2K

Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

arm: ls102xa: Add SD boot support for LS1021AQDS board

This patch adds SD boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from SD card to DDR, finally SPL transfer control to u-boot.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

arm: ls102xa: clear EPU registers for deep sleep

After wakeup from deep sleep, Clear EPU registers as early as possible
to prevent from possible issue. It's also safe to clear at normal boot.

Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

arm: ls102xa: Add Freescale LS102xA SoC support

The QorIQ LS1 family is built on Layerscape architecture,
the industry's first software-aware, core-agnostic networking
architecture to offer unprecedented efficiency and scale.

Freescale LS102xA is a set of SoCs combines two ARM
Cortex-A7 cores that have been optimized for high
reliability and pack the highest level of integration
available for sub-3 W embedded communications processors
with Layerscape architecture and with a comprehensive
enablement model focused on ease of programmability.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>

armv7: fsl: remove sata support

Remove the old implementation in order to enable DM for sata

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

nxp: ls102xa: add LS1 PSCI system suspend

The deep sleep function of LS1 platform, is mapped into PSCI system
suspend function, this patch adds implementation of it.

Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

arm: ls1021a: merge SoC specific code in a separate file

Create a soc.c file to put the code for soc special settings.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

arm: ls1021a: Add sata support on qds and twr board

Freescale ARM-based Layerscape LS102xA contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls1021aqds and ls1021atwr boards.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

arm/ls102xa: Add PSCI support for ls102xa

Base on PSCI services, implement CPU_ON/CPU_OFF for ls102xa platform.

Tested on LS1021AQDS, LS1021ATWR.
Test CPU hotplug times: 60K
Test kernel boot times: 1.2K

Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

arm: ls102xa: Add SD boot support for LS1021AQDS board

This patch adds SD boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from SD card to DDR, finally SPL transfer control to u-boot.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

arm: ls102xa: clear EPU registers for deep sleep

After wakeup from deep sleep, Clear EPU registers as early as possible
to prevent from possible issue. It's also safe to clear at normal boot.

Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

arm: ls102xa: Add Freescale LS102xA SoC support

The QorIQ LS1 family is built on Layerscape architecture,
the industry's first software-aware, core-agnostic networking
architecture to offer unprecedented efficiency and scale.

Freescale LS102xA is a set of SoCs combines two ARM
Cortex-A7 cores that have been optimized for high
reliability and pack the highest level of integration
available for sub-3 W embedded communications processors
with Layerscape architecture and with a comprehensive
enablement model focused on ease of programmability.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>