History log of /seL4-test-master/projects/seL4_libs/libsel4bench/arch_include/riscv/sel4bench/arch/sel4bench.h
Revision Date Author Comments
# 1f177036 25-Mar-2020 Siwei Zhuang <siwei.zhuang@data61.csiro.au>

libsel4bench: Use privileged HPM counter CSRs

This change is a work around for some Hifive boards which would freeze
when accessing user mode CSRs.


# 8fbe6c08 04-Mar-2020 Siwei Zhuang <siwei.zhuang@data61.csiro.au>

libsel4bench: Add event counter for riscv

Implement event counter, currently only supports sifive U540.


# a6c966ae 10-Feb-2020 Yanyan Shen <Yanyan.Shen@data61.csiro.au>

libsel4bench: Add support for RISC-V

Added initial support for RISC-V architecture.