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79da0792 |
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01-Mar-2020 |
Gerwin Klein <gerwin.klein@data61.csiro.au> |
Convert license tags to SPDX identifiers This commit also converts our own copyright headers to directly use SPDX, but leaves all other copyright header intact, only adding the SPDX ident. As far as possible this commit also merges multiple Data61 copyright statements/headers into one for consistency.
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2d362cb7 |
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11-Nov-2019 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
arm,SMP: Refactor irq_t structure for smp Explicitly create a struct definition for irq_t on SMP Arm configurations. This makes it a lot harder to mistakenly use the wrong irq encoding when moving an irq between a cnode index and hardware irq number / core. A couple areas where this was being handled incorrectly was fixed as part of the refactor. When performing an ipi for masking PPI interrupts, the idx encoding is used as it fits into a single word.
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ef8b0139 |
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18-Sep-2019 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
KernelIRQReporting: Change reserved IRQ reporting Reserved IRQ reporting would print on every received reserved IRQ. This feature is supposed to report spurious interrupts, yet most cases reserved IRQs are not spurious. We change the printing to only print if the reserved IRQ was unhandled. The intention is to allow more app configurations to leave this feature enabled in development builds.
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798fb76d |
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17-May-2017 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
mcs: call updatetimestamp and commitTime once This change refactors (and simplifies) the interactions with the scheduler on the irq path. We don't call commitTime on this path, as this call was redundant (we'll call it in the scheduler if we need to). Move up the calls to checkBudget and updateTimestamp. Avoid modifying the scheduler on the unlocked IPI path
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34c1f920 |
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03-Nov-2016 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
mcs: add periodic scheduling This commit adds periodic scheduling with sporadic servers.
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71244499 |
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31-Oct-2016 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
mcs: tickless scheduler implementation This changes the budget/remaining fields in scheduling contexts to contain timer ticks, not number of abstract sel4ticks. seL4_SchedControl_Configure now takes microseconds, not ticks. This commit is plat-independant - the platform and arch specific timer code follows in later commits.
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a6157d5d |
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18-Jul-2019 |
Sylvain Gauthier <sylvain.gauthier@data61.csiro.au> |
[SMP] Abstracted IRQ indexing to handle PPIs irq_t is now a "virtual" interrupt type that encapsulates the information of the core in case of a private interrupt. There is a couple of macros that need to be defined on the interrupt controller level to translate between virtual and hardware IRQs.
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1f84a048 |
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28-Apr-2019 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
RISC-V,PLIC: Cannot mask and unmask claimed IRQ While masking and unmasking IRQs seems to work for some IRQ sources, there are IRQ sources where masking an IRQ during a claim causes no more IRQs to be raised after the IRQ is unmasked. This change explicitly follows the claim->acknowledgement procedure that the PLIC expects.
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9dcb4706 |
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16-Jun-2019 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
arm: remove plat/machine/timer.h plat/machine/timer.h is unused on arm, so remove it and fix up the includes.
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306453e3 |
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18-Mar-2019 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
style: set min-conditional-indent to 0 Given we use braces all the time conditional indents do not make code cleaner.
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d0930f67 |
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18-Mar-2019 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
style: consistently attach return type Add attach-return-type to astyle
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63ed19c9 |
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12-Mar-2019 |
Sylvain Gauthier <sylvain.gauthier@data61.csiro.au> |
handleReservedIRQ now implemented on arch level except for pc99
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330cbfbd |
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07-Mar-2019 |
Sylvain Gauthier <sylvain.gauthier@data61.csiro.au> |
Made declaration of handleReservedIRQ optional, refactored consequently
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cddc4e6e |
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15-Nov-2017 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
Inline resetTimer for all platforms - for arm generic timer platforms, we remove resetTimer -> resetGenericTimer indirection and simply include generic_timer.h - this reduces boiler plate for platforms that share timer drivers, as they simply include the one header - there is far more timer code in the RT kernel, which motivates this change
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9d4010e0 |
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09-Nov-2017 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
Print single IRQ error `Arch_checkIRQ` already prints an error message in the case of x86. Printing the additional error message is both unnecessary, confusing as the message makes no sense on x86. As the error does make sense on ARM this commit moves the message to the arm `Arch_checkIRQ`
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afef52ac |
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03-Oct-2017 |
Matthew Brecknell <Matthew.Brecknell@data61.csiro.au> |
Check syscall irq argument before casting to irq_t The syscall now rejects all invalid inputs, whereas previously it silently truncated some invalid inputs.
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ee28936d |
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18-Jun-2017 |
Hesham Almatary <hesham.almatary@data61.csiro.au> |
SMP: Introduce ENABLE_SMP_SUPPORT - Make it more readable and less confusing compared to the 'CONFIG_MAX_NUM_NODES > 1' check
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8f713ab4 |
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16-Mar-2017 |
Hesham Almatary <hesham.almatary@data61.csiro.au> |
SELFOUR-747: SMP/x86: generalize arch-independent IPI code
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420ff03e |
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02-May-2017 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
SELFOUR-160: Add missing userError messages
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93cc22b2 |
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09-Mar-2017 |
amrzar <azarrabi@nicta.com.au> |
smp: fix bugs when stalling remote core - Restart TCB from inside the lock if it is waiting for anything other than IRQ - Only replace the TCB with idle thread if it is in ThreadState_RunningVM state Also, this makes the design generic to be shared with arm.
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53c6b524 |
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12-Jan-2017 |
Hesham Almatary <hesham.almatary@data61.csiro.au> |
SMP: Abstract architecture/platform independent parts of smp.h and ipi.h This commit is a re-arrangement of SMP directory structure to make it easier for other architectures/platforms (in general) and ARM (in particular) to add SMP support. * new include/smp directory to act as a centralised container of "shared" architecture-independent SMP headers. This makes it clearer what's needed for other architecture/platform to support SMP. * Each platform can define its own unique ipi.[h|c] that make sense, since ipi implementation is SoC/platform dependent.
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93c5f4b5 |
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24-Nov-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
Explicitly cast usages of `irq_t` types On some platforms `irq_t` is not defined as an `int` resulting in the `userError` messages failing to type check. This adds an explicit cast
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5e33a52c |
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24-Nov-2016 |
Kofi Doku Atuah <kofidoku.atuah@data61.csiro.au> |
Debugging: Add userError messages for seL4_IRQControl_Get
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f050e6a9 |
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20-Oct-2016 |
amrzar <azarrabi@nicta.com.au> |
implement layout of ipi interrupt handling
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3f9eb7c8 |
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06-Oct-2016 |
amrzar <azarrabi@nicta.com.au> |
SELFOUR-632: implement cores non-architecture dependent structres
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ce2c058f |
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06-Aug-2016 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
SELFOUR-607: inline remaining irq path functions
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9a7b1aec |
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06-Jun-2016 |
Anna Lyons <Anna.Lyons@nicta.com.au> |
Trivial: move printfs in handleReservedIRQ up. This wraps the printfs in CONFIG_IRQ_REPORTING and reduces redundancy.
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de8a7367 |
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16-Mar-2016 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
trivial: Add unlikely
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831892a4 |
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16-Mar-2016 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
trivial: Fix types when printing The type of irq_t differs per platform, this commit just forces a conversion to an int, which should be sufficient for a debug message
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06bd6e00 |
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01-Feb-2016 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
SELFOUR-420: Avoid indexing intStateIRQTable with an invalid IRQ
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bddd804a |
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06-Jan-2016 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
x86: IOAPIC/MSI syscalls Restructure the x86 interrupt handling to allow for a more flexible method of using IOAPIC and MSI interrupts. The essence of this change is to allow for the user to pick, for both IOAPIC and MSIs, which CPU vector to use. Additionally there is future support, in the API, for seL4 to eventually protect MSI interrupts with the vt-d interrupt routing tables. API behaviour for legacy systems using the PIC is preserved Part of SELFOUR-281
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a6aa7472 |
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25-Nov-2015 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
Remove redundant IRQInterruptControl invocation, and replace with a mechanism to actually decode arch specific IRQ invocations Part of SELFOUR-281
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d93699c9 |
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04-Jan-2016 |
Anna Lyons <Anna.Lyons@nicta.com.au> |
SELFOUR-114: remove duplication of seL4_MessageInfo_t, adjust naming to avoid cparser mangling
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0ecff9f3 |
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09-Nov-2015 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
unsigned int -> word_t
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1ea0c2c6 |
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16-Nov-2015 |
Stephen Sherratt <Stephen.Sherratt@nicta.com.au> |
Replaced "async endpoint" with "notification" in comments and error messages
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54603123 |
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19-Oct-2015 |
Anna Lyons <Anna.Lyons@nicta.com.au> |
SELFOUR-317: rename async endpoint to notification object, and other fallout.
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97042a0f |
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17-Jul-2014 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
Introduce 'Notification Binding': a new feature which allows a tcb to be bound to a single asynchronous endpoint.
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07a7f4c4 |
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29-Sep-2015 |
Anna Lyons <Anna.Lyons@nicta.com.au> |
generate warnings for incorrect format strings for kprintf, bring stdint.h inline for x86 and arm and fix some format strings as a consequence
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fd1c946c |
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01-Jul-2015 |
Thomas Sewell <Thomas.Sewell@nicta.com.au> |
Adjust -1 syntax for new Isabelle.
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0b162d7d |
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14-May-2015 |
Thomas Sewell <Thomas.Sewell@nicta.com.au> |
Weaken cap_async_cap cteDeleteOne assertions. It's true that the interrupt node must contain async endpoint caps, but we never proved the relevant invariant, and it doesn't change much.
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b0e9e468 |
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26-Apr-2015 |
Thomas Sewell <Thomas.Sewell@nicta.com.au> |
Ghost assertions for cteDeleteOne.
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138e8304 |
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16-Nov-2014 |
Matthew Fernandez <matthew.fernandez@nicta.com.au> |
trivial: Fix string typos.
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f2a3677d |
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28-Aug-2014 |
Joel Beeren <joel.beeren@nicta.com.au> |
ioapic: trivial: style
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ec5ff930 |
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25-Aug-2014 |
Joel Beeren <joel.beeren@nicta.com.au> |
ioapic: reverted setIRQState change
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3695d22b |
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21-Aug-2014 |
Joel Beeren <joel.beeren@nicta.com.au> |
ioapic: refactored C code and first attempt at haskell spec
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c0e9c638 |
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11-Aug-2014 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
Support IOAPIC on ia32 and modify interrupt handling to support user level setting of modes
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a318446f |
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07-Jul-2014 |
TrustworthySystems <gatekeeper@sel4.systems> |
Recommit of arm_hyp branch on release snapshot
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784a367b |
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07-Jul-2014 |
TrustworthySystems <gatekeeper@sel4.systems> |
Release cleanup
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91b7da86 |
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17-Jul-2014 |
TrusthworthySystems <gatekeeper@sel4.systems> |
Release snapshot
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