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79da0792 |
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01-Mar-2020 |
Gerwin Klein <gerwin.klein@data61.csiro.au> |
Convert license tags to SPDX identifiers This commit also converts our own copyright headers to directly use SPDX, but leaves all other copyright header intact, only adding the SPDX ident. As far as possible this commit also merges multiple Data61 copyright statements/headers into one for consistency.
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0cdd0514 |
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02-Apr-2019 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
ia32: adjustments to pass c-parser This commit updates the ia32 build to pass the c-parser. - replaces ++i with i++ - use void in functions with no parameters - add a missing typecast - remove a void cast of an unused variable It does not provide any verification guarantees about ia32 code.
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7fc45c4e |
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18-Mar-2019 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
style: set code width to 120
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306453e3 |
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18-Mar-2019 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
style: set min-conditional-indent to 0 Given we use braces all the time conditional indents do not make code cleaner.
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d0930f67 |
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18-Mar-2019 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
style: consistently attach return type Add attach-return-type to astyle
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5e6622fc |
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27-Mar-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x86: Check valid interrupt invocation first Verification needs to ensure that the invocation is valid before performing any decode steps.
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40d1cec7 |
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26-Mar-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x86: dedup isIRQActive check
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cfbb8813 |
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26-Mar-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x86: Correct IRQ vector range in error message
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afef52ac |
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03-Oct-2017 |
Matthew Brecknell <Matthew.Brecknell@data61.csiro.au> |
Check syscall irq argument before casting to irq_t The syscall now rejects all invalid inputs, whereas previously it silently truncated some invalid inputs.
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c6e2c5a1 |
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27-Sep-2017 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x86: Use irq_t for irq syscall argument That argument is in fact an irq_t type and this allows the code to more accurately reflect reality
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656cbaa1 |
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26-Sep-2017 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
Use irq_t type for argument to Arch_checkIRQ This was previously a word_t type, presumably because when the function was originally written irq_t was a word_t on the platform, this is a mistake and it is more correctly an irq_t
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9de5e2aa |
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21-Aug-2017 |
Bamboo <bamboo@keg.ertos.in.nicta.com.au> |
[STYLE_FIX]
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a9e1f517 |
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21-Aug-2017 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
SELFOUR-1062: Hide all IOMMU related code behind #ifdef guards The IOMMU implementation is not going to be verified at the moment, and so the code for it needs to be hidden from verification, which we do by #ifdef'ing it out if the IOMMU is not enabled. As a result the IOMMU configuration depends on a non verification target
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8c8b53a5 |
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21-Aug-2017 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
pc99: Define PCI helpers in a pci header instead of iospace header These helpers are generic PCI and are used outside of the iospace code
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57fa0e0f |
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07-Aug-2017 |
Hesham Almatary <hesham.almatary@data61.csiro.au> |
Share linker.h between architectures
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6eb2ea50 |
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29-Nov-2016 |
Kofi Doku Atuah <kofidoku.atuah@data61.csiro.au> |
Add userError messages
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3f9eb7c8 |
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06-Oct-2016 |
amrzar <azarrabi@nicta.com.au> |
SELFOUR-632: implement cores non-architecture dependent structres
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d507b2d3 |
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09-Feb-2016 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
SELFOUR-421 Introduce explicit device frames and untypeds Kernel objects cannot be created from device untypeds, with the exception of frames, which do not get zeroed and cannot be used as an IPC buffer. Device untypeds additionally cannot be used in the construction of ASID pools. This then changes the API to the rootserver (i.e. bootinfo) to send device untypeds instead of device frames. On ARM these device untypeds are the same as the previously exported device frame regions. On x86 PCI scanning is removed and all physical memory addresses (that are not important for kernel integrity) are released to the user. In order to have bits in the frame and untyped caps on ARM the number of software ASIDs had to be reduced from 2^18 to 2^17, and the maximum untyped size reduced from 2^31 to 2^30
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ce2c058f |
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06-Aug-2016 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
SELFOUR-607: inline remaining irq path functions
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53492824 |
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06-Jan-2016 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
x86/libsel4: Rename ia32->x86 Rename all functions, constants and types in libsel4 that are in the general x86 architecture to have an X86 name instead of an IA32 name. As libsel4 and the kernel share names this requires changing those in the kernel as well. All the original IA32 names can still be used for the moment, but are marked as deprecated.
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812a73a9 |
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01-Feb-2016 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
trivial: style
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bddd804a |
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06-Jan-2016 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
x86: IOAPIC/MSI syscalls Restructure the x86 interrupt handling to allow for a more flexible method of using IOAPIC and MSI interrupts. The essence of this change is to allow for the user to pick, for both IOAPIC and MSIs, which CPU vector to use. Additionally there is future support, in the API, for seL4 to eventually protect MSI interrupts with the vt-d interrupt routing tables. API behaviour for legacy systems using the PIC is preserved Part of SELFOUR-281
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e11bb32f |
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17-Jan-2016 |
Joel Beeren <joel.beeren@nicta.com.au> |
archirq: fix x86 invLabel
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a6aa7472 |
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25-Nov-2015 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
Remove redundant IRQInterruptControl invocation, and replace with a mechanism to actually decode arch specific IRQ invocations Part of SELFOUR-281
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d93699c9 |
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04-Jan-2016 |
Anna Lyons <Anna.Lyons@nicta.com.au> |
SELFOUR-114: remove duplication of seL4_MessageInfo_t, adjust naming to avoid cparser mangling
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0ecff9f3 |
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09-Nov-2015 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
unsigned int -> word_t
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914741ea |
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27-May-2015 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
x86: Make x86 the name of the architecture instead of IA32 IA32 is 32bit version of the x86 architecture. Whilst only IA32 is supported, much of the code is generic x86. Using a generic x86 architecture will aid in future 64bit support
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