riscv: Use full width of scause

The exception code has been defined as all non-sign bits of scause since
before 1.10, and masking will cause other exceptions 8 mod 16 to be
misinterpreted as system calls (24 is the lowest exception code reserved
for vendor extensions; 40 is reserved for standard use; the H extension
defines several exceptions above 16 but none are 8 mod 16).

Signed-off-by: Stefan O'Rear <sorear2@gmail.com>

Convert license tags to SPDX identifiers

This commit also converts our own copyright headers to directly use
SPDX, but leaves all other copyright header intact, only adding the
SPDX ident. As far as possible this commit also merges multiple
Data61 copyright statements/headers into one for consistency.

riscv: Use sscratch for per-core kernel stack

When SMP is enabled, the sscratch register is used to
contain the per-core kernel stack instead of the current
running thread. We get the current running thread from the
top of the kernel stack.

Consistent naming of FaultIP and NextIP in kernel

Always refer to the virtual register that stores the address of a fault
as FaultIP and the register that stores the return for a fault NextIP.

riscv: Place traps in text section

Ensures that the traps are in the text section, and not the boot section, allowing for
kernel memory to be safely reused.

riscv: Sanitize traps and fastpath functions

This removes warnings by fixing prototypes of various traps and fastpath functions as well
as removing the use of custom sections.

riscv: remove HARTID

[SELFOUR-1156] RISC-V Port

Experimental release that supports both RV32 and RV64