arm,check_export_arch_timer: zero unexported bits

Zero other bits in the register apart from the ones we explicitly
enable. This will prevent previously exported arch timer features from
continuing to be exported.

Signed-off-by: Kent McLeod <Kent.Mcleod@data61.csiro.au>

Convert license tags to SPDX identifiers

This commit also converts our own copyright headers to directly use
SPDX, but leaves all other copyright header intact, only adding the
SPDX ident. As far as possible this commit also merges multiple
Data61 copyright statements/headers into one for consistency.

cortex-a8: fix check_export_pmu

- read PMUSERENR_ENABLE first before updating. On the cortex-a8
(specifically omap3) not doing this would result in the kernel aborting.
- do not read DBGDSCR_ext on cortex-a8, read DBGDSCR_int. This is only
implemented in armv7.1, not armv7, and also causes the kernel to abort.

arm: remove duplicate pmu access code

Both CONFIG_ENABLE_BENCHMARKS and CONFIG_EXPORT_PMU_USER configured the
PMU on armv7 and armv8 to be accessible with different code. Use the
same code.

style: consistently attach return type

Add attach-return-type to astyle

SELFOUR-712: arm: enable user level PMU event counter on v7

ARM: Stop using SEL4_ARCH for selective compilation for armv source files

Remove many DONT_TRANSLATE markers.

The vast majority of the DONT_TRANSLATE markers in the kernel are used
to hide __asm__ statements and builtin functions
(e.g. __builtin_unreachable ()) from the C-to-Isabelle parser.

The parser now supports underscore identifiers and many __asm__ statements,
and the builtin functions are prototyped, meaning the vast majority of the
DONT_TRANSLATE markers can be dropped. The remaining markers cover functions
that must be treated specially.

Adjust left-shift which violates C standard.

The use of 0xf << 28 on a 32-bit platform violates the C standard, since these
values default to signed and the left shift causes a sign change. This also
leads to a quantity of head-scratching further down the line in the translation
check. Adjusting to 0xful solves the problem.

SELFOUR-607: inline remaining irq path functions

fix for asmrefine

Fix user access for VCNT

ARM: Add config options for exporting PMU and ARM generic timer physical count registers to PL0