Make kernel log buffer derived from cmake config

This removes the explicit CMake configuration for the kernel log buffer
and replaces it with a #define that is enabled for the required
configurations.

Signed-off-by: Curtis Millar <curtis@curtism.me>

trivial: style and comment

Signed-off-by: Oliver Scott <Oliver.Scott@data61.csiro.au>

SMMU: TLB coherency between MMU and SMMU

The kernel connects ASID used in MMU and context banks used in
SMMU, and conducts TLB invalidation on context banks if a page
entry is invalidated from MMU is also used in SMMU.

Signed-off-by: Oliver Scott <Oliver.Scott@data61.csiro.au>

Consolidate kernel virtual memory regions

Each architecture now only needs to describe the bounds of the three
memory regions: the 1:1 mapped physical memory region, the kernel ELF
region (which may or may not overlap the physical memory region) and the
device / kernel page table region.

The physical base address of the 1:1 mapped physcial memory region and
the kernel ELF region must also be specified.

The top of user addressable memory (where in the same virtual address
space as the kernel) is defined by USER_TOP.

The physic memory virtual mapping is described by PPTR_BASE and
PPTR_TOP. The base physical memory address is PADDR_BASE and is the
physical address used to map PPTR_BASE.

Don't use kernelBase when referring to the base of the 1:1 mapped
physical memory window.

The kernel ELF virtual address region is described by KERNEL_ELF_BASE
and extends until the virtual address of the symbol `ki_end` which is
created by the linker. KERNEL_ELF_PADDR_BASE is the base address of
the physical memory region used to map the kernel and is the address to
which KERNEL_ELF_BASE maps.

KERNEL_ELF_BASE and KERNEL_ELF_PADDR_BASE do not need to be aligned to a
page size boundary as they are approriately truncated during boot by the
`map_kernel_window` function.

KDEV_BASE describes the base virtual address of the kernel device region
and the region is assumed to extend to the end of virtual memory.

Note: The offset between PPTR_BASE and PADDR_BASE is used to translate
the virtual address of all untyped objects to physical addresses. This
includes device untyped objects or frame objects where the virtual
address does not fall within the 1:1 mapped physical memory region.

Signed-off-by: Curtis Millar <curtis.millar@data61.csiro.au>

Convert license tags to SPDX identifiers

This commit also converts our own copyright headers to directly use
SPDX, but leaves all other copyright header intact, only adding the
SPDX ident. As far as possible this commit also merges multiple
Data61 copyright statements/headers into one for consistency.

arm: Restrict cache flush operations in hyp mode

Cache flush operations are applied through the kernel window mapping in
hyp mode. This requires an extra check that the frame being provided is
accessible through the kernel window.

Move vcpu_switch into Arch_switchToThread

Currently the vcpu_switch function is called in the setVMRoot function
after possible early returns. In order to make sure the vcpu is
always switched, the call is moved into Arch_switchToThread before the
call to setVMRoot.

SELFOUR-161: Merge Page_Remap with Page_Map

- Remove Remap function from seL4 API for arm, x86, riscv and the
respective invocation implementation.
- Update Map as replacement for Remap
- Update manual

This allows a change of rights if the frame being mapped is already
mapped in at the given vaddr. To map a page to a different address,
unmap it first.

Co-authored-by: Hesham Almatary <hesham.almatary@data61.csiro.au>
Co-authored-by: Anna Lyons <Anna.Lyons@data61.csiro.au>
Co-authored-by: Victor Phan <Victor.Phan@data61.csiro.au>
Co-authored-by: Kent McLeod <Kent.Mcleod@data61.csiro.au>

aarch64: allow access to memory below physBase

On aarch64 physBase is the constant that points to the bottom of
physical memory (RAM).

Prior to this change the kernel window was mapped directly to physBase,
which is usually not a 0 paddr. As a consequence the kernel could not
access any memory below physBase.

This change fixes this issue by mapping the start of the kernel window
to 0 in the physical address space.

- add new constant PADDR_LOAD, the location of the kernel image in the
physical address space.
- add new constant PADDR_BASE, the start of the physical address space
(0).
- add new constant KERNEL_ELF_BASE, the location of the kernel image in
kernel virtual memory.

A consequence of this change is that on aarch64, the kernelBase constant
now points to the start of the kernel window in virtual memory, but
*not* to the start of the kernel image as these are now different.

aarch64: add support for 40-bit PA

This commit adds support for using a 40-bit physical addresses in
aarch64-hyp mode.

40-bit PA support is implemented by using a 3-stage translation, with a
13 bit page upper directory as the vspace root. PageGlobalDirectories
are not used in this configuration.

To use 40-bit PAs, platforms should set KernelArmPASizeBits40 to ON.

Co-authored-by: Yanyan Shen <yanyan.shen@data61.csiro.au>
Co-authored-by: Chris Guikema <chris.guikema@dornerworks.com>

aarch64: abstract vspace in libsel4

Depending on the physical address range the top level translation table
may be a page upper directory or a page global directory. Rename in
libsel4 the invocations on top level structures to be on an
seL4_ARM_VSpace rather than an seL4_ARM_PageGlobalDirectory.

aarch64: abstract vspace_root in vspace code

On aarch64-hyp the virtual address translation structure can differ
depending on the physical address range. This commit prepares to support
more than a single physical address range by removing the assumption
that the top-level structure in a vspace is a PGD, replacing it with the
concept of a vspace_root.

Specifically:
- add and use macros to refer to vtable bitfield generator functions
- use the existing vspace_root_t type rather than pgde_t
- pull performASIDPoolInvocation into header
- add and use VSPACE_PTR rather than PGDE_PTR
- rename decodeARMVPageGlobalDirectoryInvocation to refer to VSpace
- update comments/error messages
- rename variables

boot: refactor allocation of rootserver objects

Prior to this change, the boot process would dynamically allocate
memory for root server objects based on the order of initialisation.
Allocation was a best-fit algorithm.

This change preallocates all memory for root server objects to an
aligned untyped just after the user image. By allocating the objects in
order of size, allocation is greatly simplified and the ability to
reproduce the allocation offline based on the kernel and user image
sizes is increased.

boot: reduce duplicate code in map_kernel_frame

Reduce duplicated code by moving values that are different across
configs/attributes into their own conditionals, rather than the entire
call to pte_pte_small_new. This alters arm only.

aarch64: adjustments to pass c-parser

This commit updates the aarch64 build to pass the c-parser.

- replace 0b constants with decimal
- remove empty array definition
- replace __uint128_t with uint64_t, and double the array size
- remove variable shadowing

No further verification guarantees are provided for aarch64 code.

style: set code width to 120

style: set min-conditional-indent to 0

Given we use braces all the time conditional indents do not make code
cleaner.

style: consistently attach return type

Add attach-return-type to astyle

style: consistently align pointer with name

Run astyle with align-pointer=name

style: correct parenthesis padding

Use astyle's unpad-paren to unpad all parentheses that are not included
by pad-header, pad-oper, and pad-comma.

arm: Make Arm VCPU states per-node.

ARM: stop using plat/machine/devices.h

This header is going away and contains nothing of substance. Remove it.

AArch64 Benchmark Log buffer: Astyle formatting

AArch64: Benchmarking: Add log frame setter

AArch64,hyp: Fix tlb invalidation behavior

When deleting `ASID`s the `HWASID` would be deleted before it was used to
invalidate the TLB entries. Rearranging the order of `invalidateTLBByASID`
and `invalidateASIDEntry` should correctly invalide the entries.

aarch64: Add pgde enum for tracking hyp hw_asids

aarch64 hyp mode only has support for 8 bit hardware ASIDs. We use the
same strategy used in aarch32 for hardware asids where we maintain a
pool of hwasids that seL4 ASIDs are allocated. The allocation is stored
in the last entry of top level paging structure. This commit
encapsulates this into the bitfield specification in the same way as
aarch32.

armv8: Honour the execute-never bit in EL2.

aarch64/vspace: implement user stack tracing

armv8/hyp: Call invalidateASIDEntry

armv8/hyp: Use invalidateTLBASID/ASIDVA functions

armv8/hyp: Add ASID/TLB helper functions

armv8/hyp: Add VMID reuse code

armv8: Fix style

armv8/hyp: Flush cache by kernel VA in EL2

armv8: memzero an ASID pool with seL4_ASIDPoolBits

armv8/hyp: Switch VCPU in setVMRoot when HYP is on

armv8/hyp: Handle VM faults triggered by VCPUs

armv8/hyp: Use S2 format for userland if HYP is on

armv8/hyp: Support EL2 stage-1 for kernel VSpace

armv8/hyp: Map AP to stage-2 access permissions

armv8/hyp: Add stage-2 memory attributes

armv8: Add SMP support for aarch64

(1) Use NODE_STATE() to access per-core kernel data.
(2) Allocate kernel stack in src/arch/arm/64/head.S.
(3) Use the TPIDR_EL1 to contain the kernel stack pointer
as well as the logical core ID. The kernel stack must
be 4-KiB aligned, and the lowest 12 bits of TPIDR_EL1
are for the logical core ID.
(4) Define the LD_EX, ST_EX, and OP_WIDTH as "ldxr", "stxr",
and "w".
(5) Add irq_remote_call_ipi and irq_reschedule_ipi

armv8: change %x to %lx in kernelDataAbort

Change the type specifiers used by printf in the function
kernelDataAbort for aarch64 from %x to %lx for 64-bit data.

aarch64: Re-validate ipc buffer is not device frame

This should be redundant, but is required for verification to go throug

Declare and check IPC buffer size

Adds a named constant of the IPC buffer size bits that can be used when checking the
size/alignment of an IPC buffer. This constant has a compile time assertion to ensure
it corresponds to the actual IPC buffer

Share linker.h between architectures

Fix licenses (the rest)

[STYLE_FIX]

SELFOUR-748: ARM - Support local/remote TLB invalidation operations

[STYLE_FIX]

Avoid using bitfield generated *_ptr_new functions

These functions can cause slow down during verification C parsing and do not currently
have any proofs about them. More importantly there is no performance impact from just
calling the regular *_new functions instead

s/DEBUG/CONFIG_DEBUG_BUILD/

DEBUG definition is not supposed to be used in the kernel, rather CONFIG_DEBUG_BUILD,
which can be toggled separately to user notion of DEBUG

SELFOUR-744: ARM/SMP - Map kernel window and root task as cache-shareable

Default user PTEs/PDEs are also default to be shared. Later, we can
provide an option to allow the user not to map frames as shared.

s/D61/DATA61/ in license headers for consistency

aarch64: Initial implementation

aarch64: add preliminary folders and Makefiles