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00a9ba91 |
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12-May-2020 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
aarch32: Move tpidruro from vcpu to tcb context This register is visible to software executing at PL0 but not writeable. Storing it in the VCPU context required custom save/restore handling as it had to be explicitly handled when switching from a VCPU thread to a non-VCPU thread so that it didn't become a channel. It is possible to now update this register via seL4_TCB_WriteRegisters for software executing at PL0. This also fixes a bug where if a vcpu-thread is switched for a non-vcpu-thread and then switched to a different vcpu-thread the original vcpu-thread's copy of this register will get set to 0. Signed-off-by: Kent McLeod <Kent.Mcleod@data61.csiro.au>
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79da0792 |
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01-Mar-2020 |
Gerwin Klein <gerwin.klein@data61.csiro.au> |
Convert license tags to SPDX identifiers This commit also converts our own copyright headers to directly use SPDX, but leaves all other copyright header intact, only adding the SPDX ident. As far as possible this commit also merges multiple Data61 copyright statements/headers into one for consistency.
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b4e529ab |
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01-Jul-2019 |
Jimmy Brush <code@jimmah.com> |
trivial: arm: Improve object method docs
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5646f774 |
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20-Mar-2019 |
Curtis Millar <curtis.millar@data61.csiro.au> |
RFC-3: Update user context for ARM with thread IDs Switched appropriate naming conventions. Was using the aarch64, have switched to aarch64 names. TIPDRURW -> tpidr_el0 TPIDRURO -> tpidrro_el0 TPIDRPRW -> tpidr_el1 Switch TLS register on aarch32 from TPIDURO (tpidrro_el0) to tpidr_ro so that it can be written to from user-land. Thread ID registers tpidr_el0 have been added to the user context for aarch32 and aarch64. Only the thread ID that is writeable from EL0 is saved in the TCB and saved/restored on context switch. Thread IDs that are only changed within a VM (the read-only thread ID for exception level 0 and the thread ID for exception level 1) are stored in the VCPU and saved and stored as part of VM enable/disable. Thread IDs that are only changed with VMs have been separated out into hypervisor code.
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8fd604eb |
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23-Apr-2018 |
Adam Felizzi <a.felizzi@student.unsw.edu.au> |
manual: Added <docref> XML Tag to Doxygen Introduced a new Doxygen XML tag '<docref>'. The intention of this tag is to indicate a section of text in the Doxygen XML that will contain a reference to another section in the Manual e.g. "See \autoref<sec:x>". As other generation formats aren't aware of other chapters/sections in the manual, the <docref> encapsulation allows it to omit the text from the output. The Latex generator has been modified to continue parsing the 'docref' contents.
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3a21701a |
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28-Mar-2018 |
Yanyan Shen <yanyan.shen@data61.csiro.au> |
libsel4/arm: Move VCPU to the common interface
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72478f36 |
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02-Aug-2017 |
Hesham Almatary <hesham.almatary@data61.csiro.au> |
Manual: document mode/arm object invocations
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07f94833 |
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18-Jun-2017 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
libsel4: fix licenses - some were incorrectly marked GPL (libsel4 is BSD) - update NICTA --> DATA61 etc - fix tags D61 --> DATA61 - update year to 2017
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c2ca76a3 |
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24-May-2017 |
Stephen Sherratt <Stephen.Sherratt@data61.csiro.au> |
manual: Friendly names for arch-specific methods
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3498705f |
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23-May-2017 |
Stephen Sherratt <Stephen.Sherratt@data61.csiro.au> |
manual: Add basic names and labels to interfaces
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c7471db9 |
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23-May-2017 |
Stephen Sherratt <Stephen.Sherratt@data61.csiro.au> |
manual: Trivial whitespace
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ee75f086 |
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16-Oct-2016 |
amrzar <azarrabi@nicta.com.au> |
update #ifdef to #if in auto generated files
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f14dcdd0 |
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15-Jun-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
arm-hyp: Add conditions to invocations
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41603a26 |
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01-Jun-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
Correct merge of master
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1a1110a0 |
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14-Jan-2016 |
amrzar <azarrabi@nicta.com.au> |
Modify Kconfig and Makefile for aach32 as sel4_arch libsel4: updates to include aarch32 as sel4_arch
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