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512a0200 |
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19-Mar-2020 |
Qian Ge <qian.ge@data61.csiro.au> |
replacing all ifndef with pargma once All the kernel header files now use pargma once rather than the ifndef, as the pre-processed C files do not change while header files are protected with pargma once. This will also solve any naming issues caused by ifndef.
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79da0792 |
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01-Mar-2020 |
Gerwin Klein <gerwin.klein@data61.csiro.au> |
Convert license tags to SPDX identifiers This commit also converts our own copyright headers to directly use SPDX, but leaves all other copyright header intact, only adding the SPDX ident. As far as possible this commit also merges multiple Data61 copyright statements/headers into one for consistency.
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8c8b53a5 |
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21-Aug-2017 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
pc99: Define PCI helpers in a pci header instead of iospace header These helpers are generic PCI and are used outside of the iospace code
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d507b2d3 |
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09-Feb-2016 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
SELFOUR-421 Introduce explicit device frames and untypeds Kernel objects cannot be created from device untypeds, with the exception of frames, which do not get zeroed and cannot be used as an IPC buffer. Device untypeds additionally cannot be used in the construction of ASID pools. This then changes the API to the rootserver (i.e. bootinfo) to send device untypeds instead of device frames. On ARM these device untypeds are the same as the previously exported device frame regions. On x86 PCI scanning is removed and all physical memory addresses (that are not important for kernel integrity) are released to the user. In order to have bits in the frame and untyped caps on ARM the number of software ASIDs had to be reduced from 2^18 to 2^17, and the maximum untyped size reduced from 2^31 to 2^30
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bddd804a |
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06-Jan-2016 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
x86: IOAPIC/MSI syscalls Restructure the x86 interrupt handling to allow for a more flexible method of using IOAPIC and MSI interrupts. The essence of this change is to allow for the user to pick, for both IOAPIC and MSIs, which CPU vector to use. Additionally there is future support, in the API, for seL4 to eventually protect MSI interrupts with the vt-d interrupt routing tables. API behaviour for legacy systems using the PIC is preserved Part of SELFOUR-281
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8e15c429 |
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03-Nov-2015 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
x86: Port some of the IOMMU changes on the experimental branch This changes the IOMMU from using passthrough devices and instead directly mapping in the reserved regions that are needed for each device.
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91b7da86 |
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17-Jul-2014 |
TrusthworthySystems <gatekeeper@sel4.systems> |
Release snapshot
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