replacing all ifndef with pargma once

All the kernel header files now use pargma once rather than the ifndef,
as the pre-processed C files do not change while header files
are protected with pargma once. This will also solve any naming issues
caused by ifndef.

Convert license tags to SPDX identifiers

This commit also converts our own copyright headers to directly use
SPDX, but leaves all other copyright header intact, only adding the
SPDX ident. As far as possible this commit also merges multiple
Data61 copyright statements/headers into one for consistency.

RFC-3: Update context for x86 to use FS and GS.

TLS_BASE virtual register is replaced with FS_BASE and GS_BASE virtual
registers.

The FS_BASE and GS_BASE virtual registers are moved to the end of the
context so they need not be considered in the kernel exit and entry
implementation.

Removed tracking of ES, DS, FS, and GS segment selectors on kernel entry
and exit.

ES and DS are clobbered on kernel entry with the RPL 3 selector for a
DPL 3 linear data segment.

FS is clobbered on exit with the RPL 3 selector for the DPL 3 segment
with FS_BASE as the base. This is done on exit to reload the value from
the GDT.

GS is clobbered on exit with the RPL 3 selector for the DPL 3 segment
with GS_BASE as the base. This is done on exit to reload the value from
the GDT.

Kernel entry and exit code is refactored, simplified, and improved in
light of the above changes.

x64: update verified config to use fsgsbase instr

The verification platform for x64 relies on the fsgsbase instruction.

More standard constant name, moved ASID constants to arch generic files

Remove symlinked libsel4 files from include dir

These files can be included normally using libsel4 include paths. This
removes situations where the same file is available under different
include paths due to symlinking into different directory structures.

style: consistently attach return type

Add attach-return-type to astyle

style: consistently align pointer with name

Run astyle with align-pointer=name

x86: Separate definition for kernel vspace root

Introduces a separate definition for vspace root that the kernel runs on. Having this
be distinct from the global vspace root allows for potential future distinction
between the global root (that is copied into all user address spaces) and the address
space that the kernel runs in.

SELFOUR-1062: Hide all VT-x related code behind #ifdef guards

The VT-x implementation is not going to be verified at the moment, and so the code for
it needs to be hidden from verification, which we do by #ifdef'ing it out if the VT-x
is not enabled. As a result the VT-x configuration depends on a non verification target

SELFOUR-879: expose index and entry constants

ia32: remove unsued ia32KSGlobalPDPT and PDPT defines

SELFOUR-501: x86 - Remove PAE support

x86: Refactor tlb_bitmap to be mode generic

Refactors the TLB bitmap code to be generic across ia32 and x86-64.

x86: Refactor generic x86 pte/pde manipulation

Previously generic functions for manipulating page table and page
directory entries were placed in mode/structures.h. These are moved
to a mode/vspace.h instead so that they can use existing functions
defined in arch/vspace.h.

The x86_make_pde_mapping function is dropped in this move as it is
not used. Instead it is replaced with a function for creating an
empty mapping for whatever is the vspace root.

SELFOUR-287: 32-bit vt-x implementation

This is an implementation of vt-x for x86 kernels running in
ia32 mode.

SELFOUR-556: Rationalize BITS vs INDEX_BITS

s/PD_BITS/PD_INDEX_BITS
Current convention is to say that X_BITS is the log base 2
size of an object, not the log base 2 number of indices

SELFOUR-556: Rationalize BITS vs INDEX_BITS

s/PT_BITS/PT_INDEX_BITS
Current convention is to say that X_BITS is the log base 2
size of an object, not the log base 2 number of indices

SELFOUR-556: Rationalize BITS vs INDEX_BITS

s/ASID_POOL_BITS/ASID_POOL_INDEX_BITS
Current convention is to say that X_BITS is the log base 2
size of an object, not the log base 2 number of indices

SELFOUR-556: Rationalize BITS vs INDEX_BITS

s/PDT_BITS/PDPT_INDEX_BITS
Current convention is to say that X_BITS is the log base 2
size of an object, not the log base 2 number of indices

x86: Split some arch functions in mode headers into arch and mode portions

SELFOUR-516 Remove EXPECTED_TCB_SIZE

Explicitly check if a capability is physical or not

Previously the return value of cap_get_capPtr was compared to 0 in
sameRegionAs to emulate a check in the abstract specification that
tests if the cap is a physical cap or not. Overloading 0 results
in a scenario where a legitimate deviceUntyped's children do not
get considered to be children because they have a capPtr of 0.

This change adds and explicit function that returns whether or not
a capability is physical or not, and uses that in sameRegionAs

x86: Use IO page table size defined in libsel4

x86: Introduce support for XSAVE feature set

The XSAVE feature set is the future proof way for x86 CPUs to
manage extended CPU state. Extended state is MMX, FPU, SSE, AVX etc
registers. This is a replacement for the current FXSAVE and the
512 byte FPU region.

XSAVE introduces a few problems that this commit has to address

* The alignment of the XSAVE region is 64bytes, instead of the 16
bytes of the FXSAVE region
* XSAVE region size is dependent on the desired features, which
are detected at run time
* There are multiple variants of the XSAVE instruction that have
different potential optimizations, but are not always supported

The solutions to these are

* Re-order the FPU state and user registers in the user context
struct so that the new XSAVE region is first, and is thus
aligned to 64bytes without needing lots of padding
* Provide config options for desired features (including XSAVE
instruction variant) and required XSAVE region size. These
are checked at boot time to ensure the CPU meets these
requirements

x86: Rename ia32->x86

This is a stylistic commit to make names of variables/constants and
functions in the kernel more consistent. That is, things that are
not IA32 specific, but are generic x86, get renamed to having an
x86 name

SELFOUR-399: object sizes and globals frame addr should come from the same source

trivial: style

x86: Rename mistake usage of x86->ia32 to fix build errors

x86: Abstractions for setting up benchmarking log

ia32: Reduce total number of ASIDs from 16bits to 12bits

This change brings the ia32 api in line with the planned x64 api,
which will have 12bits of ASID. Aside from providing a consistent
API, this change also frees up bits in the frame cap that will
allow further x64 changes to be unified.

x86: Use typedef for vspace roots instead of void*

trivial: style

x86: Extract 32-bit specific vspace functions in mode/vspace.c

x86: With multi-kernel support removed make the kernel PDs etc global instead of passing them around

x86: Do not conditionally compile IOMMU code, use build/run time checks

Guarding code with #ifdef's makes even cursor testing of 'does this code compile'
difficult due to code being hidden by the pre-processor. Using config_set in
regular C if statements is performant as the compiler can trivially detect
dead code at compile time, and at -O1 and above will not even link in symbols
referenced by dead code in these blocks, so this will not bloat image size

x86: Make parts of what have become 32-bit specific headers common

The reason these were not made common to begin with is so that there
was a commit that was just a rename of these files to make any merges
with other branches that might exist easier

x86: Minimal changes to fix previous commit that renamed headers