aarch64,vcpu: Add CNTKCTL_EL1 register to vcpu_t

This register is accessible from EL1 and affects whether Generic Timer
registers are accessible from EL0. When switching out of guests, the
kernel needs to restore the correct access for native threads.

Signed-off-by: Kent McLeod <Kent.Mcleod@data61.csiro.au>

replacing all ifndef with pargma once

All the kernel header files now use pargma once rather than the ifndef,
as the pre-processed C files do not change while header files
are protected with pargma once. This will also solve any naming issues
caused by ifndef.

Convert license tags to SPDX identifiers

This commit also converts our own copyright headers to directly use
SPDX, but leaves all other copyright header intact, only adding the
SPDX ident. As far as possible this commit also merges multiple
Data61 copyright statements/headers into one for consistency.

arm: Added define for VMPIDR and VMPIDR_EL2

Added constant definitions for the VMPIDR (arm32) and VMPIDR_EL2
(arm64) registers. These being vcpu registers that can be
written, read, saved and restored. The 'Virtualization Multiprocessor
ID Register' (VMPIDR) is needed to program a vcpu's affinity during
initialisation. This is currently only exposed on SMP configurations.

Co-authored-by: Anna Lyons <anna@gh.st>

arm: Configure traps on vcpu WFE/WFI calls

Configure the ability to trap on vcpu WFE/WFI calls. If enabled,
user-level would need to schedule a future interrupt when a given
vcpu invokes a WFE/WFI instruction. This otherwise leaving the
vcpu in a disabled state. An application can choose to
disable the trap if it doesn't want to handle the instruction and
schedule a future interrupt.

arm_hyp: Save and restore vtimer state on switches

Added support for reading and writing additional virtual timer
registers for vcpu hw read and write accesses. These include the
compare value register (CNTV_CVAL) and offset register (CNTV_OFF),
each represented as two 32 bit (high and low) registers on aarch32 and
as single 64 bit registers on aarch64.

Added support for explicitly saving and restoring the virtual
timer registers when the vcpu is enabled and disabled. This
ensures when the vcpu is switched in and out, the virtual timer
registers are restored to a state that is consistent to when
it was last run.

By default the CNTVOFF register will be updated by the kernel to
accumulate the time the VCPU is not running. From the guest this will
result in the VCNT register not increasing when the VCPU is suspended.
This behavior can be turned off by disabling the
KernelArmVtimerUpdateVOffset config option.

arm_hyp: Update ArmV8 vcpu register operations

Update the register save and restore functions to use the provided
wrapper functions that are now in scope.

arm_hyp: Remove some vcpu_* wrapper functions

These functions have entirely arch specific implementations so remove
function wrapping indirection to ease maintainability.

arm_hyp: Refactor code into arch headers

Move vcpu functions that are specific to a particular Arm architecture
version into the relevant header files. Also move some generic functions
into the generic vcpu header file for use by arch specific headers.

aarch64: fix FAR_EL1 width in writeFAR

Fixes a bug where writeFAR was only writing to the low 32 bits of the
64-bit FAR_EL1 register.

aarch64: fix MRS/MSR in writeELR_EL1

Fixes a bug where writeELR_EL1 was reading from ELR_EL1 instead of
writing to it.

aarch64: Move tpidrro_el0 from vcpu to tcb context

This register is visible to software executing at EL0 but not writeable.
Storing it in the VCPU context required custom save/restore handling as
it had to be explicitly handled when switching from a VCPU thread to a
non-VCPU thread so that it didn't become a channel. It is possible to
now update this register via seL4_TCB_WriteRegisters for software
executing at EL0.

This also fixes a potential bug where if a vcpu-thread is switched for a
non-vcpu-thread and then switched to a different vcpu-thread the
original vcpu-thread's copy of this register will get set to 0.

aarch64: add support for 40-bit PA

This commit adds support for using a 40-bit physical addresses in
aarch64-hyp mode.

40-bit PA support is implemented by using a 3-stage translation, with a
13 bit page upper directory as the vspace root. PageGlobalDirectories
are not used in this configuration.

To use 40-bit PAs, platforms should set KernelArmPASizeBits40 to ON.

Co-authored-by: Yanyan Shen <yanyan.shen@data61.csiro.au>
Co-authored-by: Chris Guikema <chris.guikema@dornerworks.com>

aarch64-hyp: check PA and granule sizes

Check that the configured physical address range is supported by the
processor and that the granule size (4KiB) is supported.

trivial: properly mask vtcr macros

RFC-3: Update user context for ARM with thread IDs

Switched appropriate naming conventions.
Was using the aarch64, have switched to aarch64 names.

TIPDRURW -> tpidr_el0
TPIDRURO -> tpidrro_el0
TPIDRPRW -> tpidr_el1

Switch TLS register on aarch32 from TPIDURO (tpidrro_el0) to tpidr_ro so
that it can be written to from user-land.

Thread ID registers tpidr_el0 have been added to the user context for
aarch32 and aarch64.

Only the thread ID that is writeable from EL0 is saved in the TCB and
saved/restored on context switch.

Thread IDs that are only changed within a VM (the read-only thread ID
for exception level 0 and the thread ID for exception level 1) are
stored in the VCPU and saved and stored as part of VM enable/disable.

Thread IDs that are only changed with VMs have been separated out into
hypervisor code.

armv8: Save/restore TPIDRRO_EL0 for VCPUs

TPIDRRO_EL0 is used as IPC Buffer for seL4-native threads.
The register should be saved and restored for VCPUs.

aarch64: adjustments to pass c-parser

This commit updates the aarch64 build to pass the c-parser.

- replace 0b constants with decimal
- remove empty array definition
- replace __uint128_t with uint64_t, and double the array size
- remove variable shadowing

No further verification guarantees are provided for aarch64 code.

arm-hyp: pass ESR in handleUserLevelFault

style: consistently attach return type

Add attach-return-type to astyle

arm/hyp: Trap SMC calls.

armv8/hyp: Remove duplicated functions

armv8/hyp: Replace register strings with macros

armv8/hyp: Define control register macros

armv8/hyp: Clarify SCTLR_EL1 macros

armv8/hyp: Fix style

armv8/hyp: sharable -> shareable

armv8/hyp: Use macros to replace raw numbers

armv8/hyp: Add start level macros for 4KB granule

armv8/hyp: Add cacheability attribute macros

armv8/hyp: Add shareability attribute macros

armv8/hyp: Add translation granule size macros

armv8/hyp: Add PA size constants

armv8/hyp: Move macros to the beginning

armv8/hyp: Add read/writeVCPUReg functions

armv8/hyp: Add armv_vcpu_init function

armv8/hyp: Add armv_vcpu_disable function

armv8/hyp: Add armv_vcpu_enable function

armv8/hyp: Add armv_vcpu_boot_init

armv8/hyp: Add vcpu_init_vtcr; use 44-bit IPA/PA

armv8/hyp: Add macros to access VTCR_EL2 fields

armv8/hyp: Add arch_handleVCPUFault

armv8/hyp: Add VCPU register access functions

armv8/hyp: Add vcpu_hw_read/write_reg functions

armv8/hyp: Add functions to access registers

armv8/hyp: Add SCTLR constants for A57

armv8/hyp: Add HCR_COMMON/_NATIVE/_VCPU