replacing all ifndef with pargma once

All the kernel header files now use pargma once rather than the ifndef,
as the pre-processed C files do not change while header files
are protected with pargma once. This will also solve any naming issues
caused by ifndef.

Convert license tags to SPDX identifiers

This commit also converts our own copyright headers to directly use
SPDX, but leaves all other copyright header intact, only adding the
SPDX ident. As far as possible this commit also merges multiple
Data61 copyright statements/headers into one for consistency.

aarch64: Move tpidrro_el0 from vcpu to tcb context

This register is visible to software executing at EL0 but not writeable.
Storing it in the VCPU context required custom save/restore handling as
it had to be explicitly handled when switching from a VCPU thread to a
non-VCPU thread so that it didn't become a channel. It is possible to
now update this register via seL4_TCB_WriteRegisters for software
executing at EL0.

This also fixes a potential bug where if a vcpu-thread is switched for a
non-vcpu-thread and then switched to a different vcpu-thread the
original vcpu-thread's copy of this register will get set to 0.

mcs: timeout exceptions

- Add seL4_TCB_SetTimeoutEndpoint
- implement timeout exceptions

mcs: scheduling context donation over ipc

After this commit, threads blocked on an endpoint can recieve a
scheduling context from the thread that wakes the blocked thread.

RFC-3: Update user context for ARM with thread IDs

Switched appropriate naming conventions.
Was using the aarch64, have switched to aarch64 names.

TIPDRURW -> tpidr_el0
TPIDRURO -> tpidrro_el0
TPIDRPRW -> tpidr_el1

Switch TLS register on aarch32 from TPIDURO (tpidrro_el0) to tpidr_ro so
that it can be written to from user-land.

Thread ID registers tpidr_el0 have been added to the user context for
aarch32 and aarch64.

Only the thread ID that is writeable from EL0 is saved in the TCB and
saved/restored on context switch.

Thread IDs that are only changed within a VM (the read-only thread ID
for exception level 0 and the thread ID for exception level 1) are
stored in the VCPU and saved and stored as part of VM enable/disable.

Thread IDs that are only changed with VMs have been separated out into
hypervisor code.

Consistent naming of FaultIP and NextIP in kernel

Always refer to the virtual register that stores the address of a fault
as FaultIP and the register that stores the return for a fault NextIP.

arm: merge redundant hardware.c

hardware.c was defined for both 32 and 64 bit arm kernels. However, the
only difference in the file is the register used in setNextPC. Add this
register as a #define in registerset.h, move hardware.c to be common for
both 32- and 64-bit arm.

aarch64: adjustments to pass c-parser

This commit updates the aarch64 build to pass the c-parser.

- replace 0b constants with decimal
- remove empty array definition
- replace __uint128_t with uint64_t, and double the array size
- remove variable shadowing

No further verification guarantees are provided for aarch64 code.

Remove symlinked libsel4 files from include dir

These files can be included normally using libsel4 include paths. This
removes situations where the same file is available under different
include paths due to symlinking into different directory structures.

style: consistently align pointer with name

Run astyle with align-pointer=name

arm: Provide TLS_BASE virtual register

This commit provides a universal TLS_BASE virtual register on ARM, similar to as exists
on x86. Depending on the precise configuration this virtual register maps to a different
register
* aarch64: TPIDRURW is used for the TLS_BASE and is already declared and being saved
and restored on context switches, so this just adds TLS_BASE as an alias of it
* armv6: Has no hardware register for use for a TLS_BASE, and so the virtual register
gets stored into the globals frame
* armv7+: TPIDURO is used for TLS_BASE and so the restore paths are modified to load
TLS_BASE into it

armv8: Handle SPSR_EL1 in sanitiseRegister for VMs

armv8: Generalise ESR shift and constants

armv8: Add PSTATE_IDLETHREAD for EL2.

Fix licenses (the rest)

[STYLE_FIX]

Use OFFSETOF instead of directly using __builtin_offsetof

arm: Use unverified_compile_assert instead of manual #ifdef wrapping

libsel4: Add seL4_FastMessageRegisters

This allows benchmarks and utility code to only set registers in the ipc
buffer as required.

s/DEBUG/CONFIG_DEBUG_BUILD/

DEBUG definition is not supposed to be used in the kernel, rather CONFIG_DEBUG_BUILD,
which can be toggled separately to user notion of DEBUG

aarch64: FPU lazy context switch

s/D61/DATA61/ in license headers for consistency

aarch64: Initial implementation

aarch64: add preliminary folders and Makefiles