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512a0200 |
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19-Mar-2020 |
Qian Ge <qian.ge@data61.csiro.au> |
replacing all ifndef with pargma once All the kernel header files now use pargma once rather than the ifndef, as the pre-processed C files do not change while header files are protected with pargma once. This will also solve any naming issues caused by ifndef.
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79da0792 |
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01-Mar-2020 |
Gerwin Klein <gerwin.klein@data61.csiro.au> |
Convert license tags to SPDX identifiers This commit also converts our own copyright headers to directly use SPDX, but leaves all other copyright header intact, only adding the SPDX ident. As far as possible this commit also merges multiple Data61 copyright statements/headers into one for consistency.
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0de7fc11 |
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18-Dec-2019 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
Revert "Cache FPU enable state on all platforms" This reverts commit 186180cf309b365b45c162f7a1f5931f0fc05d7c.
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186180cf |
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11-Jul-2019 |
Curtis Millar <curtis.millar@data61.csiro.au> |
Cache FPU enable state on all platforms This change broadens the caching of the FPU enable/disable bit from arm to all platforms to ensure that on x86 time is not wasted on the fastpath disabling or enabling an already disabled/enabled FPU.
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04e51d40 |
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27-Nov-2019 |
Curtis Millar <curtis.millar@data61.csiro.au> |
Revert the recent changes to Faster FPU switch These changes need to be reverted until we can properly test the changes with all of our hardware online (currently we cannot test on x86 hardware). This reverts commit a0aeec3b304d16909619bc847197df221c73a0c4. This reverts commit af0fdc82c23f1e7e3f1e568f6987f5afd0d2150a. This reverts commit a190a14ecaae688a6b40dd0a699b8f49c2c0631e.
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e9b90f9f |
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11-Jul-2019 |
Curtis Millar <curtis.millar@data61.csiro.au> |
Cache FPU enable state on all platforms This change broadens the caching of the FPU enable/disable bit from arm to all platforms to ensure that on x86 time is not wasted on the fastpath disabling or enabling an already disabled/enabled FPU.
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3d10ef0c |
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18-Mar-2019 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
style: correct parenthesis padding Use astyle's unpad-paren to unpad all parentheses that are not included by pad-header, pad-oper, and pad-comma.
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7a20946b |
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27-Mar-2018 |
Yanyan Shen <yanyan.shen@data61.csiro.au> |
armv8: Modify enableFpu/disableFpu to support EL2
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3d20232f |
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27-Mar-2018 |
Yanyan Shen <yanyan.shen@data61.csiro.au> |
armv8: Add function isFpuEnabled
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6b9238a7 |
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27-Mar-2018 |
Yanyan Shen <yanyan.shen@data61.csiro.au> |
armv8: Add disableFpuEL0 This function disables FPU access for EL0 only.
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e36e9cea |
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27-Mar-2018 |
Yanyan Shen <yanyan.shen@data61.csiro.au> |
armv8: Add enableFpuEL01 The function enables FPU access for both EL0 and EL1.
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b6f5329f |
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27-Mar-2018 |
Yanyan Shen <yanyan.shen@data61.csiro.au> |
armv8/hyp: Add EL2 FPU functions enableTrapFpu: enable trapping any FPU related instructions to EL2. disableTrapFpu: disable trapping FPU instructions to EL2.
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64d576fb |
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12-Jun-2017 |
Hesham Almatary <hesham.almatary@data61.csiro.au> |
SELFOUR-806: aarch32 - Implement lazy FP save/restore This commit implements lazy FP save/restore mechanism, required for user threads when they use the FPU. The following caveats take place: * Only support synchronous exceptions. No support for asynchronous ones. * VFP opcodes are used instead of normal instructions to discard compiler warnings/errors. * Support is limited to specific ARM subarchitectures we support and tested this commit on. * Disable the FPU by default if users are not using it to avoid channels. * FPU support is not verified yet. * Will not work properly if using a VM that's running besides other VMs/threads that are using the FPU.
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40c61e5c |
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18-Jun-2017 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
Fix licenses (the rest)
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8610061a |
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23-Feb-2017 |
amrzar <azarrabi@nicta.com.au> |
aarch64: FPU lazy context switch
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