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dc83859f |
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30-Oct-2020 |
Bamboo <bamboo@bitbucket.ts.data61.csiro.au> |
Release 12.0.0 Update VERSION Update CHANGES Signed-off-by: Oliver Scott <Oliver.Scott@data61.csiro.au>
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af98be7d |
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02-Nov-2020 |
Oliver Scott <Oliver.Scott@data61.csiro.au> |
trivial: update changes file Some of the changes from the last release should have been in the 12.0.0 release. Signed-off-by: Oliver Scott <Oliver.Scott@data61.csiro.au>
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#
b86bce2d |
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14-Oct-2020 |
Kent McLeod <kent@kry10.com> |
aarch64,cortex-a53,hyp: Reduce seL4_UserTop value This ensures that no frames can be mapped that would overwrite the currently stored VMID for the vspace. Signed-off-by: Kent McLeod <kent@kry10.com>
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#
00a9ba91 |
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12-May-2020 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
aarch32: Move tpidruro from vcpu to tcb context This register is visible to software executing at PL0 but not writeable. Storing it in the VCPU context required custom save/restore handling as it had to be explicitly handled when switching from a VCPU thread to a non-VCPU thread so that it didn't become a channel. It is possible to now update this register via seL4_TCB_WriteRegisters for software executing at PL0. This also fixes a bug where if a vcpu-thread is switched for a non-vcpu-thread and then switched to a different vcpu-thread the original vcpu-thread's copy of this register will get set to 0. Signed-off-by: Kent McLeod <Kent.Mcleod@data61.csiro.au>
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b0816d2d |
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03-Mar-2020 |
Gerwin Klein <gerwin.klein@data61.csiro.au> |
Release docs owned by Data61 under CC-BY-SA-4.0 CC-BY-SA-4.0 is a more appropriate license for documentation than BSD or GPL.
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0e05f416 |
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23-Jun-2019 |
Alison Felizzi <Alison.Felizzi@data61.csiro.au> |
arm: Configure traps on vcpu WFE/WFI calls Configure the ability to trap on vcpu WFE/WFI calls. If enabled, user-level would need to schedule a future interrupt when a given vcpu invokes a WFE/WFI instruction. This otherwise leaving the vcpu in a disabled state. An application can choose to disable the trap if it doesn't want to handle the instruction and schedule a future interrupt.
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#
71d636f8 |
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20-Jun-2019 |
Alison Felizzi <Alison.Felizzi@data61.csiro.au> |
arm_hyp: Save and restore vtimer state on switches Added support for reading and writing additional virtual timer registers for vcpu hw read and write accesses. These include the compare value register (CNTV_CVAL) and offset register (CNTV_OFF), each represented as two 32 bit (high and low) registers on aarch32 and as single 64 bit registers on aarch64. Added support for explicitly saving and restoring the virtual timer registers when the vcpu is enabled and disabled. This ensures when the vcpu is switched in and out, the virtual timer registers are restored to a state that is consistent to when it was last run. By default the CNTVOFF register will be updated by the kernel to accumulate the time the VCPU is not running. From the guest this will result in the VCNT register not increasing when the VCPU is suspended. This behavior can be turned off by disabling the KernelArmVtimerUpdateVOffset config option.
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f795e7c0 |
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23-Jun-2019 |
Alison Felizzi <Alison.Felizzi@data61.csiro.au> |
arm: New virtual PPI event fault type This commit introduces a new fault type, seL4_Fault_VPPIEvent. This change means the kernel can reserve PPI interrupts and virtualise them via delivering the irq to the active vcpu through a specific fault. This enables multiplexing PPI IRQs across multiple VCPUS which requires correctly masking and unmasking the IRQ depending on which VCPU is running. A new VCPU invocation, seL4_ARM_VCPU_AckVPPI is also added for acknowledging the handling of the IRQ. This takes an IRQ as a parameter but will only accept IRQ numbers that are sent as VPPIEvent faults. Co-authored-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au> Co-authored-by: Kent McLeod <Kent.Mcleod@data61.csiro.au>
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4ef43d50 |
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21-Nov-2019 |
G. Branden Robinson <Branden.Robinson@data61.csiro.au> |
CHANGES: improve introduction Recast introductory paragraphs to better describe the document and characterise the intended audience. Move information intended for document maintainers and kernel engineers to a comment. Add guidance for engineers so they better know when and how to update this document. (Thanks to Kent for the discussion!) The `docs/sel4_release` page is not a set of release notes per se, more like a feature grid and release history; describe it differently. Style document title as a top-level heading.
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ff216025 |
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18-Nov-2019 |
Bamboo <bamboo@bitbucket.ts.data61.csiro.au> |
Release 11.0.0 Update VERSION Update CHANGES
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eec474dc |
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20-Nov-2019 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
Update CHANGES with changes since last release Try to add all missing changes that affect the seL4 interface.
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9abe8a4f |
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15-Jul-2019 |
Oliver Scott <Oliver.Scott@data61.csiro.au> |
add support for rockpro64 Kernel support for 64 bit rockpro board. Dts was taken from the linux kernel.
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4efbd436 |
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09-Oct-2019 |
Sylvain Gauthier <sylvain.gauthier@data61.csiro.au> |
Updated CHANGES file Updated CHANGES file to add virt support.
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1cb5887a |
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09-Oct-2019 |
Yanyan Shen <Yanyan.Shen@data61.csiro.au> |
trivial: Update CHANGES
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a4d6bf85 |
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28-Feb-2016 |
amrzar <Amirreza.Zarrabi@data61.csiro.au> |
SELFOUR-161: Merge Page_Remap with Page_Map - Remove Remap function from seL4 API for arm, x86, riscv and the respective invocation implementation. - Update Map as replacement for Remap - Update manual This allows a change of rights if the frame being mapped is already mapped in at the given vaddr. To map a page to a different address, unmap it first. Co-authored-by: Hesham Almatary <hesham.almatary@data61.csiro.au> Co-authored-by: Anna Lyons <Anna.Lyons@data61.csiro.au> Co-authored-by: Victor Phan <Victor.Phan@data61.csiro.au> Co-authored-by: Kent McLeod <Kent.Mcleod@data61.csiro.au>
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#
8234026c |
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16-Sep-2019 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
aarch64: Move tpidrro_el0 from vcpu to tcb context This register is visible to software executing at EL0 but not writeable. Storing it in the VCPU context required custom save/restore handling as it had to be explicitly handled when switching from a VCPU thread to a non-VCPU thread so that it didn't become a channel. It is possible to now update this register via seL4_TCB_WriteRegisters for software executing at EL0. This also fixes a potential bug where if a vcpu-thread is switched for a non-vcpu-thread and then switched to a different vcpu-thread the original vcpu-thread's copy of this register will get set to 0.
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7798b476 |
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06-Sep-2019 |
Anna Lyons <anna@gh.st> |
aarch64: allow access to memory below physBase On aarch64 physBase is the constant that points to the bottom of physical memory (RAM). Prior to this change the kernel window was mapped directly to physBase, which is usually not a 0 paddr. As a consequence the kernel could not access any memory below physBase. This change fixes this issue by mapping the start of the kernel window to 0 in the physical address space. - add new constant PADDR_LOAD, the location of the kernel image in the physical address space. - add new constant PADDR_BASE, the start of the physical address space (0). - add new constant KERNEL_ELF_BASE, the location of the kernel image in kernel virtual memory. A consequence of this change is that on aarch64, the kernelBase constant now points to the start of the kernel window in virtual memory, but *not* to the start of the kernel image as these are now different.
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#
1387bfeb |
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21-Aug-2019 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
mcs: Update CHANGES file Adds that mcs was merged into the changes file. More detailed release notes will be included in the next release version.
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4a37703c |
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28-Mar-2019 |
Chris Guikema <chris.guikema@dornerworks.com> |
cortex-53: enable virtualization extensions This is possible now that the kernel supports 40 bit PAs.
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#
49d3f220 |
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25-Jun-2019 |
Sylvain Gauthier <sylvain.gauthier@data61.csiro.au> |
[SMP/Debug] New syscall to send arbitrary SGIs Created a new syscall, seL4_DebugSendIPI for ARM to send arbitrary SGIs (software generated interrupts) to arbitrary cores. As SGIs are specifically PPIs (private interrupts), this syscall effectively allows to trigger PPIs on arbitrary cores, for debug/testing purposes.
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#
7900b6dc |
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17-Feb-2019 |
Yanyan Shen <yanyan.shen@data61.csiro.au> |
aarch64: Add initial Arm FVP platform config This platform assumes 2 clusters of A57 processors as described in tools/dts/fvp.dts. This configuration is for running on FVP simulators.
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#
051d32be |
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26-Mar-2019 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
Add initial i.MX8M Quad evk 64-bit Support This adds support for the 64-bit i.MX8M Quad evaluation kit. Currently only AArch64 EL1 is supported.
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#
60e64bd5 |
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01-Jul-2019 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
trivial: Update CHANGES for GICv3
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#
a06690fb |
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04-Apr-2019 |
Curtis Millar <curtis.millar@data61.csiro.au> |
Update CHANGES to reflect RFC-3 Changes.
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7c8938bd |
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23-Jun-2019 |
James Ye <james.ye@data61.csiro.au> |
trivial: CHANGES: document am335x updates
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#
90c49746 |
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19-Jun-2019 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
x86/ept: return correct MappingFailedLookupLevel Prior to this change, seL4_MappingFailedLookupLevel() would retrun '22' after any failed EPT mapping operation. This change fixes this to return the correct amount of unresolved bits in the address.
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#
5fac9e81 |
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29-Apr-2019 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
config: make root cnode size 4k minimum The previous minimum (4) was actually too small to fit more than 1 capability, which would not allow the kernel to boot. A 4K minimum means on 32-bit, an 8 size is the minimum (256 slots) and on 64-bit, 7 (128 slots). In addition to being a more practical minimum, this also allows for simplification of the boot code for future commits.
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#
f3fbf855 |
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29-Apr-2019 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
libsel4: add seL4_VspaceBits This constant represents the size of the root page table.
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#
6a31a57e |
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25-Nov-2018 |
Simon Shields <simon.shields@data61.csiro.au> |
ARM: optionally pass bootloader DTB to userspace We now support receiving a DTB from the ELF loader and passing it on to userspace in extra bootinfo. We still support booting without a DTB, though - the device tree address is set to zero in the boot code and no extra bootinfo region is provided.
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#
d8c9069c |
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25-Nov-2018 |
Simon Shields <simon.shields@data61.csiro.au> |
add FDT extended bootinfo type FDT is not platform specific (and used on RISC-V and ARM), so this bootinfo type isn't either.
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#
a16cc57e |
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28-Mar-2019 |
James Ye <james.ye@data61.csiro.au> |
Add Odroid-C2 support Add support for the Hardkernel Odroid-C2 board. Co-Authored-By: Anna Lyons <Anna.Lyons@data61.csiro.au>
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#
c274850b |
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12-Mar-2019 |
Jasper Lowell <jasper.lowell@data61.csiro.au> |
Updated CHANGES with Clang support
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#
34ce52e2 |
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18-Feb-2019 |
Oliver Scott <Oliver.Scott@data61.csiro.au> |
serial-refactor: Refactor kernel serial drivers Have added a drivers/serial folder to kernel, where all serial drivers will be kept. The point is to have the the dts parsed and generate cmake to include the right uart.c file prefixed with the compatibility. Have removed all io.c from plat and includes from plat/config.cmake and updated CHANGES file.
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#
8440f033 |
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09-Jan-2019 |
Simon Shields <simon.shields@data61.csiro.au> |
hardware_gen: pull interrupts from DTS This adds support for extracting interrupt numbers from DTS to the hardware header file generator, so that the majority of the per-platform interrupt listings can be removed.
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#
0ac07923 |
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09-Dec-2018 |
Simon Shields <simon.shields@data61.csiro.au> |
arm: generate memory region tables from dts This change adds infrastructure to automatically generate the physBase macro, the avail_p_regs array, and the dev_p_regs array based on a device tree. Platforms can opt-in to using this by adding DTS files to the KernelDTSList variable. The Python script uses the hardware.yml file to determine which devices in the device tree are of interest to the kernel and should be hidden from userspace and instead mapped into the kernel. Note that currently the kernel mappings are not (yet) generated, however most of the infrastructure needed to make that happen is present.
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#
e7bc2748 |
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11-Dec-2018 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
Update CHANGES with details of Aarch64-hyp
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76faadc9 |
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06-Dec-2018 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
Add seL4_UserTop and move kernelBase to the arch level - seL4_UserTop is a new constant which represents the top of virtual memory available to user level - this commit also rationalises several constants (USER_TOP, kernelBase) and moves them to the arch level, such that ports only need to define seL4_UserTop.
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#
2f43788b |
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10-Sep-2018 |
Thibaut PĂ©rami <thibaut.perami@ens.fr> |
libsel4: add seL4_CapRightsBits
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#
3df00ea4 |
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22-Apr-2018 |
Thibaut Perami <thibaut.perami@data61.csiro.au> |
SELFOUR-6: Add GrantReply to the rights system. GrantReply is a new access right added to endpoint capabilities, which allows seL4_Call to be used on those capabilities (specifically, it allows reply caps *only* to be granted across endpoints). Prior to the addition of GrantReply, endpoint capabilities required the Grant access right, which allowed any arbitrary capabilitiy to be transferred over an endpoint. Using GrantReply, systems can now be constructed where threads using seL4_Call over an endpoint do not need to be in the same security subsystem.
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#
57e5417c |
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11-Nov-2018 |
Bamboo <bamboo@bitbucket.ts.data61.csiro.au> |
Release 10.1.1 Update VERSION Update CHANGES
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#
a3c341ad |
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06-Nov-2018 |
Bamboo <bamboo@bitbucket.ts.data61.csiro.au> |
Release 10.1.0 Update VERSION Update CHANGES
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#
567c3044 |
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05-Nov-2018 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
CHANGES: update for upcoming release Add notes for changes missed during development.
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896e8644 |
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15-Oct-2018 |
Peter Chubb <Peter.Chubb@data61.csiro.au> |
TX2: Add initial TX2 support See CHANGES and https://docs.sel4.systems/Hardware/ for more information
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eb0553fa |
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27-Jun-2018 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
SELFOUR-1491: add seL4_IRQCOntrol_GetTrigger Add a new invocation which allows an irq handler capability to be obtained with a specific trigger method (edge or level). Obtaining this capability modifies the GIC state.
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fa4568ed |
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10-Aug-2018 |
Thomas Sewell <Thomas.Sewell@data61.csiro.au> |
Drop SEL4_PACKED from types used by seL4. It has become clear that the 'packed' GCC attribute affects the memory semantics of C in a way that the verification tools do not understand. The bootinfo types are used by kernel boot code (not currently verified, but covered by binary verification) and should not use this attribute. This is a source-compatible but not binary-compatible change.
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#
5c7f7844 |
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27-May-2018 |
Bamboo <bamboo@keg.ertos.in.nicta.com.au> |
Release 10.0.0 Update VERSION Update CHANGES
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#
6eb7e2f9 |
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28-May-2018 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
CHANGES: Add missing word `create`
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#
ed8753a1 |
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27-May-2018 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
CHANGES: Add note about new build system
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0128dd10 |
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27-May-2018 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
CHANGES: Add riscv-32 support to CHANGES file
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#
f754da33 |
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24-May-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x86: Document IOPortControl in CHANGES
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#
0dd40b6c |
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17-Apr-2018 |
Bamboo <bamboo@keg.ertos.in.nicta.com.au> |
Release 9.0.1 Update VERSION Update CHANGES
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#
d4bb778d |
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17-Apr-2018 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
Revert "Release 9.0.1" This reverts commit 77e157a98432d564ba173551e8f70032227cd9d9.
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#
77e157a9 |
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17-Apr-2018 |
Bamboo <bamboo@keg.ertos.in.nicta.com.au> |
Release 9.0.1 Update VERSION Update CHANGES
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#
0b7d80c9 |
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11-Apr-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
riscv: Document architecture in CHANGES
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c5184b80 |
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12-Apr-2018 |
Matthew Brecknell <Matthew.Brecknell@data61.csiro.au> |
update CHANGES for `label` field of `seL4_MessageInfo`
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23832600 |
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12-Apr-2018 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
docsite: Update url
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f58d22af |
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10-Apr-2018 |
Bamboo <bamboo@keg.ertos.in.nicta.com.au> |
Release 9.0.0 Update VERSION Update CHANGES
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#
f12d6fdc |
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20-Mar-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
Increase seL4_TCBBits ready for alignment increase The alignment of the tcb_t portion of a TCB object is going to be increased, this will cause the total TCB size to overflow in some cases. This updates the definition of seL4_TCBBits such that TCBs will be large enough after the alignment change.
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#
33398f21 |
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24-Jan-2018 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
SELFOUR-331: add seL4_TCB_SetSchedParams This allows the prio and mcp to be set in one system call.
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#
46ddf1ab |
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21-Feb-2018 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
Change prio, mcp to seL4_Word from Uint8_t Although seL4_MaxPrio does fit into 8 bits, making the argument 8 bits is not saving us anything.
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#
05b83acd |
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14-Dec-2017 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
SELFOUR-1016: Require auth cap to set prio/mcp This fixes confused deputy problem when setting priorities/mcps.
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#
ce2efb33 |
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18-Feb-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
Remove archInfo from bootinfo With extended bootinfo providing a more flexible and extensible form of archInfo this member can be retired.
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7887cb24 |
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18-Feb-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x86: Store TSC frequency in extended bootinfo header
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9a10cfac |
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18-Feb-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x86: Define tsc frequency bootinfo header
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b1e799a4 |
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28-Jan-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x86: Config option for RSB flush on context switch This option can be enabled to prevent a user from performing a Spectre like attack on another user through polluting the RSB.
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#
2423c620 |
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28-Jan-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x86: Config option for branch prediction barrier on context switch This option can be enabled to prevent a user from performing a Spectre like attack on another user through polluting the indirect branch predictor.
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#
f0594ac9 |
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28-Jan-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x86: Implement IBRS based Spectre mitigations Provides the ability to enable the IBRS hardware Spectre mitigation strategies, as well as completes the software mitigation by disabling jump tables in compilation. The hardware mitigations are largely provided "for completeness" in the hopes that they eventually become less expensive. For the moment there is no reason to turn on any beyond STIBP if running in multicore
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#
69a20e2c |
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16-Jan-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
Document x86-64 Meltdown change
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#
7f33209a |
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16-Jan-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
Move changes to correct section The dangerous MSR interface was not in the 8.0.0 release and so should have been listed in the upcoming release section
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#
eec02fd2 |
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15-Jan-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x86: Dangerous read/write MSR interface Provides a syscall interface for reading and writing arbitrary MSR values. This is being introduced as an alternative to the DebugRun, as the main purpose of debug run is for modifying the performance monitoring events via read/write MSR.
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#
425ceb9c |
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16-Jan-2018 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
Update VERSION file to 8.0.0-dev
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#
396315f3 |
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16-Jan-2018 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
Release 8.0.0 Update version file Update release notes
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#
d40e361c |
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15-Jan-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x86: Document PMC export in CHANGES
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#
7441a843 |
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30-Nov-2017 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x86: Describe mbi2 framebuffer support in CHANGES
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#
cfe5ce68 |
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27-Nov-2017 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
Update release notes for latest changes
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#
8108c811 |
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02-Oct-2017 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
libsel4: Remove bitfield type unifying Guard and Badge construction Using the bitfield generator to treat guards and badges as a union type can be convenient, but it requires reserving a bit in the data for the bitfield run time type information. This type information is not needed by the kernel as it knows implicitly whether the passed data is a badge or a guard based on the kind of cap being operated on. However, with the type information present we cannot pass a word sized piece of data to the kernel. The solution here is to go back to using a plain seL4_Word as the type for invocations that want a capdata and let the user either construct a badge as a plain word, or use the seL4_CNode_CapData bitfield for constructing a guard, although they have to manually extract the word representation out of it.
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#
7832d033 |
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04-Oct-2017 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x86: Update changes file for multiboot2 changes
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#
cceedf23 |
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04-Oct-2017 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
Clarify how the upcoming release notes in the CHANGES file work
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f8bac1a9 |
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04-Oct-2017 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
Update CHANGES file to be wordwrapped
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dc90e77e |
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02-Oct-2017 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
Updates CHANGES file for added zynq platform
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#
750d040a |
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04-Sep-2017 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
Add CHANGES file The purpose of this file is to track changes as they are made to the kernel in order make writing release notes easier and tracking source or binary level API breakages.
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