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21d4e03e |
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02-Jul-2020 |
Michael Yoo <Michael.Yoo@data61.csiro.au> |
Revert "libplatsupport: hifive ltimer refactor" This reverts commit c0c8ddcfac95a09b50e82cfa88367145d7aeaa5e.
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c0c8ddcf |
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18-May-2020 |
Michael Yoo <michael.yoo@data61.csiro.au> |
libplatsupport: hifive ltimer refactor - Introduce two new helper functions `helper_fdt_alloc_simple`, `create_ltimer_simple` These are only used when there's 1 reg and 1 irq to register. - Refactor hifive timers to use these helper functions. - Nit: init time_h explicitly instead of being calloc'd
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794e4497 |
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20-Aug-2019 |
Damon Lee <Damon.Lee@data61.csiro.au> |
libplatsupport: Reset hifive pwm prescaler The prescaler was not reset each time a new timeout was set. The bitwise OR operation would take the previous prescaler bits and mess up the prescaler setting for the new timeout. This commit resets the prescaler so that the timeouts will now work as intended.
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aaf83339 |
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29-Jul-2019 |
Curtis Millar <curtis.millar@data61.csiro.au> |
hifive: Use interrupt bits to correclty get time The sticky bit and the interrupt pending bits can be used to ensure that the correctu current time is read even if the interrupt to increment the time has not been handled.
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c78427f2 |
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29-Jul-2019 |
Curtis Millar <curtis.millar@data61.csiro.au> |
hifive: Correctly configure timer registers The PWM device on the hifive will trigger interrupts if whenever the compare registers are equal to the counter (even if the counter is not enabled). As such, unused timer registers are set to the maximum value and the inactive timer is set to 0 when not in use. Additionally, the interrupt pending flags can be written to in order to acknowledge the interrupts.
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aafc51ff |
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08-Jul-2019 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
libplatsupport: Add hifive serial and pwm drivers This implements the required drivers to pass sel4test
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