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7cc1142c |
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08-Apr-2020 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
aarch64,vcpu: Add CNTKCTL_EL1 register to vcpu_t This register is accessible from EL1 and affects whether Generic Timer registers are accessible from EL0. When switching out of guests, the kernel needs to restore the correct access for native threads. Signed-off-by: Kent McLeod <Kent.Mcleod@data61.csiro.au>
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79da0792 |
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01-Mar-2020 |
Gerwin Klein <gerwin.klein@data61.csiro.au> |
Convert license tags to SPDX identifiers This commit also converts our own copyright headers to directly use SPDX, but leaves all other copyright header intact, only adding the SPDX ident. As far as possible this commit also merges multiple Data61 copyright statements/headers into one for consistency.
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91f8ff70 |
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06-Feb-2020 |
Rafal Kolanski <rafal.kolanski@data61.csiro.au> |
arm-hyp: check vtimer irq state before masking Without an invariant, during verification we no longer know that the virtual timer irq is not inactive in restore_virt_timer, necessitating an extra check.
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01514662 |
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22-Jan-2020 |
Rafal Kolanski <rafal.kolanski@data61.csiro.au> |
arm-hyp: provide MODIFIES info for DONT_TRANSLATE C parser cascades up DONT_TRANSLATE blocking modifies proofs, unless some kind of spec is provided. This makes the claim that the timer register getters don't modify any global state, and the setters modify only state verification does not care about.
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71d636f8 |
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20-Jun-2019 |
Alison Felizzi <Alison.Felizzi@data61.csiro.au> |
arm_hyp: Save and restore vtimer state on switches Added support for reading and writing additional virtual timer registers for vcpu hw read and write accesses. These include the compare value register (CNTV_CVAL) and offset register (CNTV_OFF), each represented as two 32 bit (high and low) registers on aarch32 and as single 64 bit registers on aarch64. Added support for explicitly saving and restoring the virtual timer registers when the vcpu is enabled and disabled. This ensures when the vcpu is switched in and out, the virtual timer registers are restored to a state that is consistent to when it was last run. By default the CNTVOFF register will be updated by the kernel to accumulate the time the VCPU is not running. From the guest this will result in the VCNT register not increasing when the VCPU is suspended. This behavior can be turned off by disabling the KernelArmVtimerUpdateVOffset config option.
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bdc56112 |
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20-Nov-2017 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
arm: tickless generic timer implementation Update the generic timer to implement the MCS kernels tickless timer driver API and update all platforms that use the arm generic timers: - bcm2837 - exynos5 - hikey - imx7 - odroidc2 - tk1 - tx1 - tx2 - zynq7000 Also move the generic timer constants to machine.h to avoid a circular dependency.
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9dcb4706 |
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16-Jun-2019 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
arm: remove plat/machine/timer.h plat/machine/timer.h is unused on arm, so remove it and fix up the includes.
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391b717d |
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08-Apr-2019 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
arm: generic_timer -> drivers/timer/arm_generic - move generic_timer.h to drivers/timer/arm_generic.h - update all configs that use it.
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2fbdf188 |
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06-Mar-2019 |
Oliver Scott <Oliver.Scott@data61.csiro.au> |
timer-refactor: Move kernel timers and rename This change moves all arm platform timers to drivers/timer and renames them to the compatibility string specified in the dts. Now the correct timer is included at build time based on the dts, this follows the same pattern as the serial-refactor. Have moved the arm generic_timer and priv_timer into the timer folder and updated cmake configs appropriately.
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