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ab3d8c44 |
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18-Nov-2020 |
Curtis Millar <curtis.millar@data61.csiro.au> |
riscv: Map devices with large pages on 32 & 64-bit For 64-bit, this adds a 2nd-level page table for mapping devices using 2MiB frames instead of 1GiB frames. The boot mapping and hardware header generator have also been fixed to correctly report the number of large frames needed for devices rather than only reporting the first. The frame size is also specified correctly (rather than assuming mapping with 4KiB frames). This likely fixes an issue whereby only the first 4KiB frame of a device was reserved but the remaining region of that kernel device could be mapped at user level. Signed-off-by: Curtis Millar <curtis.millar@data61.csiro.au>
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509f855a |
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01-Aug-2020 |
Stefan O'Rear <sorear@fastmail.com> |
riscv: Delete unused function Signed-off-by: Stefan O'Rear <sorear@fastmail.com>
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79da0792 |
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01-Mar-2020 |
Gerwin Klein <gerwin.klein@data61.csiro.au> |
Convert license tags to SPDX identifiers This commit also converts our own copyright headers to directly use SPDX, but leaves all other copyright header intact, only adding the SPDX ident. As far as possible this commit also merges multiple Data61 copyright statements/headers into one for consistency.
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2cd80a8c |
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29-May-2019 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
Document internal machine/interrupt.h interface Every platform has to implement a standard set of interrupt interfaces that the kernel uses to interract with a machine's interrupt controller. Providing a single header file for each of these functions provides a single location to document their behavior.
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66bc2b17 |
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05-Nov-2019 |
Victor Phan <Victor.Phan@data61.csiro.au> |
rename KDEV_PPTR/PPTR_KDEV to KDEV_BASE This is the virtual address for the start of the kernel device mapping region.
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b5c56244 |
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07-Oct-2019 |
Simon Shields <simon.shields@data61.csiro.au> |
Create device untypeds at boot for all arches Currently on x86 device untypeds are generated by passing the entire address space minus any parts that are reserved by the kernel or that are "real" memory (e.g. kernel image, physical RAM). On ARM and RISC-V, device untypeds were generated at compile-time from a device tree. This patch moves ARM and RISC-V to use the same approach as x86, and moves the code from x86 into a common location that's shared between the three architectures. Co-Authored-By: Anna Lyons <anna@gh.st>
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0a6df5fc |
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18-Aug-2019 |
Yanyan Shen <yanyan.shen@data61.csiro.au> |
riscv: Remove IPI functions when SMP is off Remove ipi_get_irq() and ipi_clear_irq() when SMP is not enabled.
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860ab65d |
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06-Aug-2019 |
Yanyan Shen <yanyan.shen@data61.csiro.au> |
trivial: Fix compile error when debug is off
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79e0613c |
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06-Aug-2019 |
Yanyan Shen <yanyan.shen@data61.csiro.au> |
riscv: Add IPI support and SMPify IRQ-related code Add IPI support and SMPify IRQ-related code.
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c83a7710 |
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06-Aug-2019 |
Yanyan Shen <yanyan.shen@data61.csiro.au> |
riscv: Print SIP for spurious interrupts Add a bit more information for spurious interrupts.
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d1a0de41 |
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06-Aug-2019 |
Yanyan Shen <yanyan.shen@data61.csiro.au> |
riscv: Split IRQ init to platform and local Split IRQ init code to platform-code and per-hart code.
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e19fddbb |
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16-Jul-2019 |
Curtis Millar <curtis.millar@data61.csiro.au> |
mcs: Remove timer init and reset from RISC-V The timer init and reset are not needed to initialise the clock for MCS in RISC-V.
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557f8d4f |
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16-Jul-2019 |
Curtis Millar <curtis.millar@data61.csiro.au> |
riscv: Relocate read time to header Move the RISCV function to read the current time to the header file so that it can be inlined for MCS.
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8b4ed994 |
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23-Jun-2019 |
Siwei Zhuang <siwei.zhuang@data61.csiro.au> |
RISCV: Add Hifive unleashed platform This change adds support for Hifive unleashed board. It also removes the outdated hifive suport from the spike platform.
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375a98c8 |
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19-Jun-2019 |
Siwei Zhuang <siwei.zhuang@data61.csiro.au> |
CMake: Generate device headers from DTS for spike The DTS compilation was arm platforms only. Moving it to the top level config file, making it available to RISCV platforms. The generated files are almost identical with minor differences. A new argument(--arch) is added to the hardware_gen.py for the differences.
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01b73622 |
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27-May-2019 |
Curtis Millar <curtis.millar@data61.csiro.au> |
Consistent naming of FaultIP and NextIP in kernel Always refer to the virtual register that stores the address of a fault as FaultIP and the register that stores the return for a fault NextIP.
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d0930f67 |
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18-Mar-2019 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
style: consistently attach return type Add attach-return-type to astyle
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83ba0847 |
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20-Feb-2018 |
Hesham Almatary <hesham.almatary@unsw.edu.au> |
[SELFOUR-1156] RISC-V Port Experimental release that supports both RV32 and RV64
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