#
4af32319 |
|
18-Nov-2020 |
Rafal Kolanski <rafal.kolanski@data61.csiro.au> |
arm: remove binary literals in GIC v3 code C parser used by verification does not allow binary literals as they are not part of the C99 standard. Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
|
#
4fc3a2df |
|
29-Jun-2020 |
Yanyan Shen <yshen@cog.systems> |
gicv3: Group the targets by AFF1 For the targets in the same AFF1, ICC_SGI1R_EL1 is written once for the targets. Signed-off-by: Yanyan Shen <yshen@cog.systems>
|
#
208c9131 |
|
29-Jun-2020 |
Yanyan Shen <yshen@cog.systems> |
gicv3: Generalise SGI code Remove the special handing for MT bit since AFF1 is included when sending IPI. Signed-off-by: Yanyan Shen <yshen@cog.systems>
|
#
393ce463 |
|
27-Jun-2020 |
Yanyan Shen <yshen@cog.systems> |
gicv3: Include cluster ID when sending IPIs The MPIDR_AFFI1 field is included when sending IPIs, since cores for IPI targets can be in a different cluster. Signed-off-by: Yanyan Shen <yshen@cog.systems>
|
#
79da0792 |
|
01-Mar-2020 |
Gerwin Klein <gerwin.klein@data61.csiro.au> |
Convert license tags to SPDX identifiers This commit also converts our own copyright headers to directly use SPDX, but leaves all other copyright header intact, only adding the SPDX ident. As far as possible this commit also merges multiple Data61 copyright statements/headers into one for consistency.
|
#
2d362cb7 |
|
11-Nov-2019 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
arm,SMP: Refactor irq_t structure for smp Explicitly create a struct definition for irq_t on SMP Arm configurations. This makes it a lot harder to mistakenly use the wrong irq encoding when moving an irq between a cnode index and hardware irq number / core. A couple areas where this was being handled incorrectly was fixed as part of the refactor. When performing an ipi for masking PPI interrupts, the idx encoding is used as it fits into a single word.
|
#
6746428a |
|
05-Jul-2019 |
Anna Lyons <anna@gh.st> |
arm,gicv3: implement setIRQTarget This allows SPIs to be routed to different cores.
|
#
e4562cc2 |
|
05-Jul-2019 |
Anna Lyons <anna@gh.st> |
arm,gicv3: implement ipi_send_target This function enables ipis to be sent between cores. Co-authored-by: Yanyan Shen <yanyan.shen@data61.csiro.au>
|
#
0f139e7f |
|
25-Jul-2019 |
Anna Lyons <anna@gh.st> |
arm,gicv3: update to use virtual ppi irqs This commit updates the gic_v3 driver to translate virtual irqs to hardware irq numbers, which enables PPI support for SMP.
|
#
794aad98 |
|
25-Jul-2019 |
Anna Lyons <anna@gh.st> |
arm,gicv3: consisent sgi/ppi checks This commit brings the gic_v3 is_sgi and is_ppi checks in line with gicv2 making the code more consistent. It also removes unneccessary conditionals in the checks, as is_sgi is always called before is_ppi so the lower bounds checks are not required.
|
#
0d3692ed |
|
25-Jul-2019 |
Anna Lyons <anna@gh.st> |
arm,gicv3: use SPI_START This removes a redundant constant to use one from the gic_common header.
|
#
dd6b8cb6 |
|
09-Jul-2019 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
gic_v3: Support for aarch32
|
#
466455f3 |
|
20-Feb-2019 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
gic: Move common GIC definitions to shared header Share definitions between gic_pl390.h and gic_v3.h.
|
#
b6184ef1 |
|
20-Feb-2019 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
gic_v3: Check rwp register value before time Checking the value of the register write pending bit before reading from the generic timer is an optimisation
|
#
759a8c76 |
|
20-Feb-2019 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
gic_v3: Add setIRQTrigger This enables invocations to change the trigger mode of an IRQ.
|
#
53f08062 |
|
25-Feb-2019 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
gic_v3: Change EOI mode to drop and deactivation TODO: Decide what EOI mode we want.
|
#
ca01c8d9 |
|
20-Feb-2019 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
gic_v3: Rename driver from gic_500 This driver should be compatible with GIC v3 implementations
|