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512a0200 |
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19-Mar-2020 |
Qian Ge <qian.ge@data61.csiro.au> |
replacing all ifndef with pargma once All the kernel header files now use pargma once rather than the ifndef, as the pre-processed C files do not change while header files are protected with pargma once. This will also solve any naming issues caused by ifndef.
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79da0792 |
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01-Mar-2020 |
Gerwin Klein <gerwin.klein@data61.csiro.au> |
Convert license tags to SPDX identifiers This commit also converts our own copyright headers to directly use SPDX, but leaves all other copyright header intact, only adding the SPDX ident. As far as possible this commit also merges multiple Data61 copyright statements/headers into one for consistency.
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76faadc9 |
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06-Dec-2018 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
Add seL4_UserTop and move kernelBase to the arch level - seL4_UserTop is a new constant which represents the top of virtual memory available to user level - this commit also rationalises several constants (USER_TOP, kernelBase) and moves them to the arch level, such that ports only need to define seL4_UserTop.
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02ca6a80 |
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14-Jul-2017 |
Robbie VanVossen <robert.vanvossen@dornerworks.com> |
Added 32-bit support for the zynqmp. The Zynq UltraScale+ MPSoC (PLAT zynqmp) is a Multi-Processor SOC made by Xilinx that has a quad-core Cortex-A53, a dual-core Cortex-R5 and an FPGA. This adds 32-bit, single-core support on the the Cortex-A53 cluster.
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