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512a0200 |
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19-Mar-2020 |
Qian Ge <qian.ge@data61.csiro.au> |
replacing all ifndef with pargma once All the kernel header files now use pargma once rather than the ifndef, as the pre-processed C files do not change while header files are protected with pargma once. This will also solve any naming issues caused by ifndef.
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79da0792 |
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01-Mar-2020 |
Gerwin Klein <gerwin.klein@data61.csiro.au> |
Convert license tags to SPDX identifiers This commit also converts our own copyright headers to directly use SPDX, but leaves all other copyright header intact, only adding the SPDX ident. As far as possible this commit also merges multiple Data61 copyright statements/headers into one for consistency.
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76faadc9 |
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06-Dec-2018 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
Add seL4_UserTop and move kernelBase to the arch level - seL4_UserTop is a new constant which represents the top of virtual memory available to user level - this commit also rationalises several constants (USER_TOP, kernelBase) and moves them to the arch level, such that ports only need to define seL4_UserTop.
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07f94833 |
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18-Jun-2017 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
libsel4: fix licenses - some were incorrectly marked GPL (libsel4 is BSD) - update NICTA --> DATA61 etc - fix tags D61 --> DATA61 - update year to 2017
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4b491dcf |
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23-Mar-2017 |
Kofi Doku Atuah <kofidoku.atuah@data61.csiro.au> |
SELFOUR-836: arm-hyp: Config option for saving/loading vs trapping debug state Provides a configuration option for enabling HDCR.TD* traps, or saving and loading debug state on VCPU switches. Currently verification only plans to support the trap setting. As this option complicates all of the #ifdef's related to debug registers even further, abstractions for enabling/disabling each individual piece of the debug code for different configuration options are also implemented. Part of these refactored #ifdef guards was to remove the guards completely from libsel4 around the definitions of the number of breakpoints and watchpoints.
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725d0dac |
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20-Mar-2017 |
Kofi Doku Atuah <kofidoku.atuah@data61.csiro.au> |
SELFOUR-836: Disable debug context save/restore between VMs This patch disables the debug register state save and restore on ARM-hyp, such that Guest VMs can now interfere with one another and trigger one another for certain limited scenarios. This will be undone later on.
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469bdd61 |
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04-Jan-2017 |
Kofi Doku Atuah <kofidoku.atuah@data61.csiro.au> |
ARM-HYP: Add support for save/restore of debug registers As things are now, the Guest VMs can modify the debug registers at will from non-secure PL1, and the kernel does nothing to ensure that guest VM debug coprocessor registers are preserved. This is a preliminary patch that simply hooks into vcpu_save and saves the CPU's debug coprocessor registers when saving VCPU state. For restoring the debug registers on switching to a VCPU, we just re-use restore_user_debug_context, which is already called in restore_user_context. (Restore_user_context is called by c_handle_vcpu_fault()). Specifically, we modify the used_breakpoints_bf so that restore_user_debug_context() will always pop all the debug context. This patch only covers the breakpoint and watchpoint registers, and it doesn't cover the entire debug coprocessor, which is another conversation.
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eccaae51 |
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20-Feb-2017 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
s/D61/DATA61/ in license headers for consistency
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b90238d0 |
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19-Oct-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
Replace #pragma once with include guards
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bebfcf6d |
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23-Jun-2016 |
Kofi Doku Atuah <kofi.dokuatuah@nicta.com.au> |
SELFOUR-499: X86, ARM: Add userspace invocations for hardware debugging This commit implements the body of SELFOUR-499. The API exposes the x86 DR0-7 and ARM coprocessor 14 features to userspace by virtualizing them as context- switched registers in the TCB. Implemented as TCB invocations. This feature is only built when CONFIG_HARDWARE_DEBUG_API is selected. * Add low-level support routines for setting, unsetting, getting, enabling and disabling breakpoints. * Add support for single-stepping as well. ^ Single-stepping is not supported on ARMv6 since the hardware doesn't have support. ^ ARM implements single-stepping as instruction breakpoints configured to fault on every instruction -- this is achieved through the "mismatch" mode, which is only supported from ARMv7 onwards. * Also support explicit software break requests, a la "BKPT" and "INT $3". * New invocations: * seL4_TCB_SetBreakpoint(). * seL4_TCB_GetBreakpoint(). * seL4_TCB_UnsetBreakpoint(). * seL4_TCB_ConfigureSingleStepping(). * New constants: ^ Event types: ^ seL4_InstructionBreakpoint. ^ seL4_DataBreakpoint. ^ seL4_SoftwareBreakRequest. ^ Access types: ^ seL4_BreakOnRead. ^ seL4_BreakOnWrite. ^ seL4_BreakOnReadWrite. ^ Exports: ^ seL4_NumHWBreakpoints. ^ seL4_NumExclusiveBreakpoints. ^ seL4_NumExclusiveWatchpoints. ^ seL4_NumDualFunctionMonitors. ^ seL4_FirstBreakpoint. ^ seL4_FirstWatchpoint. ^ seL4_FirstDualFunctionMonitor. See documentation in the seL4 API manual.
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